EDI88130LPS17TC datasheet, PDF

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EDI88130LPS17TC: DescriptionStandard SRAM, 128KX8, 17ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32; Categorystorage; File Size256KB，9 Pages; ManufacturerWhite Microelectronics

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EDI88130LPS17TC Overview

Standard SRAM, 128KX8, 17ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32

EDI88130LPS17TC Parametric

Parameter Name	Attribute value
Maker	White Microelectronics
package instruction	0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32
Reach Compliance Code	unknown
Is Samacsys	N
Maximum access time	17 ns
JESD-30 code	R-CDIP-T32
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal location	DUAL
Base Number Matches	1

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EDI88130CS

HI-RELIABILITY PRODUCT

128Kx8 Monolithic SRAM, SMD 5962-89598

FEATURES

Access Times of 15*, 17, 20, 25, 35, 45, 55ns

Battery Back-up Operation

• 2V Data Retention (EDI88130LPS)

, CS

& OE Functions for Bus Control

Inputs and Outputs Directly TTL Compatible

Organized as 128Kx8

Commercial, Industrial and Military Temperature Ranges

Thru-hole and Surface Mount Packages JEDEC Pinout

•

32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102)

32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9)

32 lead Ceramic SOJ (Package 140)

32 pad Ceramic Quad LCC (Package 12)

32 pad Ceramic LCC (Package 141)

32 lead Ceramic Flatpack (Package 142)

The EDI88130CS is a high speed, high performance, 128Kx8 bits

monolithic Static RAM.

An additional chip enable line provides system memory security

during power down in non-battery backed up systems and memory

banking in high speed battery backed systems where large mul-

tiple pages of memory are required.

The EDI88130CS has eight bi-directional input-output lines to

provide simultaneous access to all bits in a word.

A low power version, EDI88130LPS, offers a 2V data retention

function for battery back-up applications.

Military product is available compliant to MIL-PRF-38535.

* 15ns access time is advanced information, contact factory for availability.

Single +5V (±10%) Supply Operation

FIG. 1

PIN CONFIGURATION

32 DIP

32 SOJ

32 CLCC

32 FLATPACK

32 QUAD LCC

PIN DESCRIPTION

I/O

0-7

0-16

, CS

TOP VIEW

Data Inputs/Outputs

Address Inputs

Write Enable

Chip Selects

Output Enable

Power (+5V

±10%)

Ground

Not Connected

TOP VIEW

A16

A14

A12

AØ

I/OØ

I/O1

I/O2

32 V

31 A15

30 CS2

29 WE

28 A13

27 A8

26 A9

25 A11

24 OE

23 A10

22 CS1

21 I/O7

20 I/O6

19 I/O5

18 I/O4

17 I/O3

I/O

BLOCK DIAGRAM

Memory Array

I/O

Ø-16

Address

Buffer

Address

Decoder

I/O

Circuits

I/O

Ø-7

February 2000 Rev. 9

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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