HD74LV132ATELL-E datasheet, PDF

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HD74LV132ATELL-E: DescriptionLV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, PDSO14, TSSOP-14; Categorylogic; File Size86KB，11 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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HD74LV132ATELL-E Overview

LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, PDSO14, TSSOP-14

HD74LV132ATELL-E Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Renesas Electronics Corporation
Parts packaging code	TSSOP
package instruction	TSSOP-14
Contacts	14
Reach Compliance Code	compliant
Is Samacsys	N
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.006 A
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	17.5 ns
propagation delay (tpd)	23 ns
Certification status	Not Qualified
Schmitt trigger	YES
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	4.4 mm
Base Number Matches	1

HD74LV132ATELL-E Related Products

	HD74LV132ATELL-E	HD74LV132AFPEL-E
Description	LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, PDSO14, TSSOP-14	LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, PDSO14, SOP-14
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation
Parts packaging code	TSSOP	SOIC
package instruction	TSSOP-14	SOP-14
Contacts	14	14
Reach Compliance Code	compliant	compliant
series	LV/LV-A/LVX/H	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e4	e4
length	5 mm	10.06 mm
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	NAND GATE	NAND GATE
MaximumI(ol)	0.006 A	0.006 A
Humidity sensitivity level	1	1
Number of functions	4	4
Number of entries	2	2
Number of terminals	14	14
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SOP
Encapsulate equivalent code	TSSOP14,.25	SOP14,.3
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE
method of packing	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	17.5 ns	17.5 ns
propagation delay (tpd)	23 ns	23 ns
Certification status	Not Qualified	Not Qualified
Schmitt trigger	YES	YES
Maximum seat height	1.1 mm	2.2 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2 V	2 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	1.27 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	20	20
width	4.4 mm	5.5 mm
Base Number Matches	1	1

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