PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
Rev. 7 — 10 December 2013
Product data sheet
1. General description
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for
SMBus and I
2
C-bus applications. The PCA9557 consists of an 8-bit input port register,
8-bit output port register, and an I
2
C-bus/SMBus interface. It has low current consumption
and a high-impedance open-drain output pin, IO0.
The system master can enable the PCA9557’s I/O as either input or output by writing to
the configuration register. The system master can also invert the PCA9557 inputs by
writing to the active HIGH polarity inversion register. Finally, the system master can reset
the PCA9557 in the event of a time-out by asserting a LOW in the reset input.
The power-on reset puts the registers in their default state and initializes the
I
2
C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to
occur without de-powering the part.
2. Features and benefits
Lower voltage, higher performance migration path for the PCA9556
8 general purpose input/output expander/collector
Input/output configuration register
Active HIGH polarity inversion register
I
2
C-bus and SMBus interface logic
Internal power-on reset
Noise filter on SCL/SDA inputs
Active LOW reset input
3 address pins allowing up to 8 devices on the I
2
C-bus/SMBus
High-impedance open-drain on IO0
No glitch on power-up
Power-up with all channels configured as inputs
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant inputs/outputs
0 kHz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Three packages offered: SO16, TSSOP16, HVQFN16
NXP Semiconductors
PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
3. Ordering information
Table 1.
Ordering information
Topside
marking
9557
PCA9557D
PCA9557
Package
Name
HVQFN16
SO16
TSSOP16
Description
plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 4
4
0.85 mm
plastic small outline package; 16 leads; body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT629-1
SOT109-1
SOT403-1
Type number
PCA9557BS
PCA9557D
PCA9557PW
3.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PCA9557BS,118
PCA9557D,112
PCA9557D,118
PCA9557PW
PCA9557PW,112
PCA9557PW,118
Package
Packing method
Minimum Temperature range
order
quantity
6000
1000
2500
2400
2500
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
Type number
PCA9557BS
PCA9557D
HVQFN16
SO16
SO16
TSSOP16
TSSOP16
Reel 13” Q1/T1
*Standard mark SMD
Standard marking
* IC’s tube - DSC bulk pack
Reel 13” Q1/T1
*Standard mark SMD
Standard marking
* IC’s tube - DSC bulk pack
Reel 13” Q1/T1
*Standard mark SMD
4. Block diagram
PCA9557
A0
A1
A2
8-bit
SCL
SDA
INPUT
FILTER
I
2
C-BUS/SMBus
CONTROL
write pulse
V
DD
V
SS
RESET
002aad275
INPUT/
OUTPUT
PORTS
read pulse
POWER-ON
RESET
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
Fig 1.
Block diagram of PCA9557
PCA9557
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 10 December 2013
2 of 30
NXP Semiconductors
PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
data from
shift register
configuration
register
data from
shift register
write configuration
pulse
D
FF
CK
Q
D
FF
IO0
write pulse
CK
output port
register
input port
register
D
FF
read pulse
CK
polarity inversion
register
data from
shift register
write polarity
pulse
D
FF
CK
002aad277
Q
output port
register data
Q
ESD protection
diode
V
SS
Q
input port
register data
Q
polarity inversion
register data
On power-up or reset, all registers return to default values.
Fig 2.
Simplified schematic of IO0
PCA9557
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 10 December 2013
3 of 30
NXP Semiconductors
PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
data from
shift register
configuration
register
data from
shift register
write configuration
pulse
D
FF
CK
Q
D
FF
Q
Q
output port
register data
V
DD
ESD protection
diode
IO1 to IO7
write pulse
CK
output port
register
input port
register
D
FF
read pulse
CK
polarity inversion
register
data from
shift register
write polarity
pulse
D
FF
CK
002aad278
ESD protection
diode
V
SS
Q
input port
register data
Q
polarity inversion
register data
On power-up or reset, all registers return to default values.
Fig 3.
Simplified schematic of IO1 to IO7
PCA9557
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 10 December 2013
4 of 30
NXP Semiconductors
PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
5. Pinning information
5.1 Pinning
SCL
SDA
A0
A1
A2
IO0
IO1
V
SS
1
2
3
4
16 V
DD
15 RESET
14 IO7
13 IO6
SCL
SDA
A0
A1
A2
IO0
IO1
V
SS
1
2
3
4
5
6
7
8
002aad273
16 V
DD
15 RESET
14 IO7
13 IO6
12 IO5
11 IO4
10 IO3
9
IO2
PCA9557D
5
6
7
8
002aad272
12 IO5
11 IO4
10 IO3
9
IO2
PCA9557PW
Fig 4.
Pin configuration for SO16
Fig 5.
13 RESET
Pin configuration for TSSOP16
16 SDA
15 SCL
terminal 1
index area
A0
A1
A2
IO0
1
2
14 V
DD
12 IO7
11 IO6
PCA9557BS
3
4
5
6
7
8
10 IO5
9
IO4
IO1
V
SS
IO2
IO3
002aad274
Transparent top view
Fig 6.
Pin configuration for HVQFN16
5.2 Pin description
Table 3.
Symbol
SCL
SDA
A0
A1
A2
IO0
IO1
PCA9557
Pin description
Pin
SO16, TSSOP16
1
2
3
4
5
6
7
HVQFN16
15
16
1
2
3
4
5
serial clock line
serial data line
address input 0
address input 1
address input 2
input/output 0 (open-drain)
input/output 1
© NXP B.V. 2013. All rights reserved.
Description
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 7 — 10 December 2013
5 of 30