LTC2289IUP#PBF datasheet, PDF - EEWORLD Datasheet

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LTC2289IUP#PBF: DescriptionAnalog to Digital Converter - ADC Dual 10-bit, 80Msps Low Power ADC; CategoryAnalog mixed-signal IC converter; File Size646KB，24 Pages; ManufacturerADI; Websitehttps://www.analog.com; Environmental Compliance

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LTC2289IUP#PBF Overview

Analog to Digital Converter - ADC Dual 10-bit, 80Msps Low Power ADC

LTC2289IUP#PBF Parametric

Parameter Name	Attribute value
Brand Name	Analog Devices Inc
Is it lead-free?	Contains lead
Is it Rohs certified?	conform to
package instruction	HVQCCN,
Contacts	64
Manufacturer packaging code	05-08-1705
Reach Compliance Code	compliant
Is Samacsys	N
Maximum analog output voltage	1.9 V
Minimum analog output voltage	1 V
Converter type	D/A CONVERTER
Enter bit code	OFFSET BINARY, 2'S COMPLEMENT BINARY
Input format	PARALLEL
JESD-30 code	S-PQCC-N64
JESD-609 code	e3
length	9 mm
Maximum linear error (EL)	0.0586%
Humidity sensitivity level	1
Number of digits	10
Number of functions	2
Number of terminals	64
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	0.8 mm
Nominal settling time (tstl)	0.0059 µs
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	9 mm
Base Number Matches	1

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LTC2289

Dual 10-Bit, 80Msps

Low Noise 3V ADC

FEATURES

■

DESCRIPTIO

■

Integrated Dual 10-Bit ADCs

Sample Rate: 80Msps

Single 3V Supply (2.7V to 3.4V)

Low Power: 422mW

61.6dB SNR at 70MHz Input

85dB SFDR at 70MHz Input

110dB Channel Isolation at 100MHz

Multiplexed or Separate Data Bus

Flexible Input: 1V

P-P

to 2V

P-P

Range

575MHz Full Power Bandwidth S/H

Clock Duty Cycle Stabilizer

Shutdown and Nap Modes

Pin Compatible Family

105Msps: LTC2282 (12-Bit), LTC2280 (10-Bit)

80Msps: LTC2294 (12-Bit), LTC2289 (10-Bit)

65Msps: LTC2293 (12-Bit), LTC2288 (10-Bit)

40Msps: LTC2292 (12-Bit), LTC2287 (10-Bit)

25Msps: LTC2291 (12-Bit), LTC2286 (10-Bit)

64-Pin (9mm

9mm) QFN Package

The LTC

2289 is a 10-bit 80Msps, low noise 3V dual A/D

converter designed for digitizing high frequency, wide

dynamic range signals. The LTC2289 is perfect for

demanding imaging and communications applications

with AC performance that includes 61.6dB SNR and 85dB

SFDR for signals well beyond the Nyquist frequency.

DC specs include

±0.1LSB

INL (typ),

±0.1LSB

DNL (typ)

and

±0.6LSB

INL,

±0.5LSB

DNL over temperature. The

transition noise is a low 0.08LSB

RMS

A single 3V supply allows low power operation. A separate

output supply allows the outputs to drive 0.5V to 3.6V

logic. An optional multiplexer allows both channels to

share a digital output bus.

A single-ended CLK input controls converter operation. An

optional clock duty cycle stabilizer allows high perfor-

mance at full speed for a wide range of clock duty cycles.

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

APPLICATIO S

■

Wireless and Wired Broadband Communication

Imaging Systems

Spectral Analysis

Portable Instrumentation

TYPICAL APPLICATIO

ANALOG

INPUT A

INPUT

S/H

10-BIT

PIPELINED

ADC CORE

OUTPUT

DRIVERS

D9A

•

–

D0A

OGND

SNR (dBFS)

CLK A

CLOCK/DUTY CYCLE

CONTROL

MUX

CLOCK/DUTY CYCLE

CONTROL

CLK B

ANALOG

INPUT B

INPUT

S/H

–

10-BIT

PIPELINED

ADC CORE

OUTPUT

DRIVERS

D9B

•

D0B

OGND

2289 TA01

SNR vs Input Frequency,

–1dB, 2V Range, 80Msps

100

150

INPUT FREQUENCY (MHz)

200

2289 TA02

2289fa

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Is it Rohs certified?	conform to	incompatible	incompatible	incompatible	conform to	incompatible	conform to	conform to
package instruction	HVQCCN,	HVQCCN,	9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64	9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64	HVQCCN,	HVQCCN,	HVQCCN,	HVQCCN,
Reach Compliance Code	compliant	not_compliant	not_compliant	not_compliant	compliant	not_compliant	compliant	compliant
Converter type	D/A CONVERTER	D/A CONVERTER	ADC, PROPRIETARY METHOD	ADC, PROPRIETARY METHOD	D/A CONVERTER	D/A CONVERTER	D/A CONVERTER	D/A CONVERTER
JESD-30 code	S-PQCC-N64	S-PQCC-N64	S-PQCC-N64	S-PQCC-N64	S-PQCC-N64	S-PQCC-N64	S-PQCC-N64	S-PQCC-N64
JESD-609 code	e3	e0	e0	e0	e3	e0	e3	e3
length	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm
Maximum linear error (EL)	0.0586%	0.0586%	0.0586%	0.0586%	0.0586%	0.0586%	0.0586%	0.0586%
Humidity sensitivity level	1	1	1	1	1	1	1	1
Number of digits	10	10	10	10	10	10	10	10
Number of functions	2	2	1	1	2	2	2	2
Number of terminals	64	64	64	64	64	64	64	64
Maximum operating temperature	85 °C	85 °C	85 °C	70 °C	85 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HVQCCN	HVQCCN	HVQCCN	HVQCCN	HVQCCN	HVQCCN	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	235	235	235	260	235	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Nominal supply voltage	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	MATTE TIN	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	Matte Tin (Sn)	MATTE TIN
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	20	20	20	30	20	30	30
width	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm
Maximum analog output voltage	1.9 V	1.9 V	-	-	1.9 V	1.9 V	1.9 V	1.9 V
Minimum analog output voltage	1 V	1 V	-	-	1 V	1 V	1 V	1 V
Enter bit code	OFFSET BINARY, 2'S COMPLEMENT BINARY	OFFSET BINARY, 2\'S COMPLEMENT BINARY	-	-	OFFSET BINARY, 2'S COMPLEMENT BINARY	OFFSET BINARY, 2\'S COMPLEMENT BINARY	OFFSET BINARY, 2'S COMPLEMENT BINARY	OFFSET BINARY, 2'S COMPLEMENT BINARY
Input format	PARALLEL	PARALLEL	-	-	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Nominal settling time (tstl)	0.0059 µs	0.0059 µs	-	-	0.0059 µs	0.0059 µs	0.0059 µs	0.0059 µs

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