Low Phase-Noise, Low-Power
Programmable PhiClock™ Generator
9FGV1004
Datasheet
Description
The 9FGV1004 is a member of IDT's PhiClock™ programmable
clock generator family. The 9FGV1004 provides 1 copy each of 2
integer-related frequencies, 2 copies of a fractional or
spread-spectrum frequency and two copies of the crystal
reference input. Two select pins allow for hardware selection of
the desired configuration, or two I
2
C bits all easy software
selection of the desired configuration. The user may configure any
one of the four OTP configurations as the default when operating
in I
2
C mode. Four unique I
2
C addresses are available, allowing
easy I
2
C access to multiple components.
Features
▪
▪
▪
▪
▪
1.8V to 3.3V core V
DD
and V
DDREF
Individual 1.8V to 3.3V V
DDO
for each output pair
Supports HCSL, LVDS and LVCMOS I/O standards
Supports LVPECL and CML logic with easy AC coupling – see
application note
AN-891
for alternate terminations
HCSL utilizes IDT's LP-HCSL technology for improved
performance, lower power and higher integration:
— Programmable output impedance of 85 or 100Ω
On-board OTP supports up to 4 complete configurations
Configuration selected via strapping pins or I
2
C
< 125mW at 1.8V, < 230mW at 3.3V with outputs running at
100MHz
4 programmable I
2
C addresses: D0/D1, D2/D3, D4/D5, D6/D7
read/write
Programmable spread spectrum modulation frequency and
amount
Supported by IDT
Timing Commander™
software
Space saving 4 × 4 mm 24-VFQFPN
Typical Applications
▪
▪
▪
▪
▪
HPC
Storage
10G/25G Ethernet
Fiber Optic Modules
SSDs
▪
▪
▪
▪
▪
▪
▪
Output Features
▪
4 programmable output pairs
▪
2 integer output frequencies and 1 fractional or spread
spectrum output frequency per configuration
▪
2 LVCMOS REF outputs
▪
10MHz–325MHz output frequency (LVDS or LP-HCSL), integer
configuration
▪
10MHz–200MHz output frequency (LVCMOS), integer
configuration
▪
10MHz–156.25MHz output frequency, fractional or spread
spectrum configuration
Key Specifications
▪
331fs rms typical phase jitter (OUT[3:0] outputs) at 156.25MHz
(12kHz–20MHz)
▪
PCIe Gen 1–4 compliant (spread spectrum off)
▪
PCIe Gen 1–3 compliant (spread spectrum on)
PCIe Clocking Architectures
Supported
▪
Common Clocked (CC)
▪
Independent Reference without spread spectrum (SRnS)
VDDAp
REF 1
REF 0
VDDREFp
INT
DIV
OUT3#
OUT3
VDDO 3
OUT2#
OUT2
VDDO 2
OUT1#
OUT1
VDDO 1
OUT0#
OUT0
VDDO 0
Block Diagram
VDDDp
XIN/CLKIN
XO
OTP_VPP
OSC
INT
PLL
INT
DIV
vSEL_I2C#
^SEL0/SCL
^SEL1/SDA
^OEB
^OEA
SMBus
Engine
Factory
Configuration
FOD
(SSC)
Control Logic
Internal terminations are available when LPHCSL output format is selected .
EPAD /GND
©2018 Integrated Device Technology, Inc.
1
May 30, 2018
9FGV1004 Datasheet
Table 1. OE Mapping
OE[B:A]
00
01
10
11
OUT0
Running
Running
Stopped
Running
OUT1
Stopped
Running
Stopped
Running
OUT2
Running
Stopped
Running
Running
OUT3
Stopped
Stopped
Running
Running
REF0
Running
Running
Running
Running
REF1
Running
Running
Running
Running
Pin Assignments
Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package – Top View
vREF0_SEL_I2C#
Note: The order
of OUT3 is
reversed from
OUT[0:2]
18 VDDO2
17 OUT2
16 OUT2#
15 VDDO1
14 OUT1
13 OUT1#
7
VDDDp
8
^OEB
9 10 11 12
OTP_VPP
VDDO0
OUT0#
OUT0
VDDREFp
VDDO3
VDDAp
OUT3#
24 23 22 21 20 19
XIN/CLKIN 1
XO 2
REF1 3
^SEL0/SCL 4
^SEL1/SDA 5
^OEA 6
9FGV1004
connect
EPAD to GND
4 × 4 mm 24-VFQFPN, 0.5mm pitch
^ prefix indicates internal 120kOhm pull-up resistor
v prefix indicates internal 120kOhm pull-down resistor
Pin Descriptions
Table 2. Pin Descriptions
Number
1
2
3
4
5
6
XO
REF1
Name
XIN/CLKIN
Type
Input
Output
Output
Input
I/O
Input
Crystal input or reference clock input.
Crystal output.
LVCMOS reference output.
OUT3
Description
^SEL0/SCL
^SEL1/SDA
^OEA
Select pin for internal frequency configurations/I
2
C clock pin. Function is determined by
state of SEL_I2C# upon power-up. This pin has an internal pull-up.
Select pin for internal frequency configurations/I
2
C data pin. Function is determined by state
of SEL_I2C# upon power-up. This pin has an internal pull-up.
Active high input for enabling outputs. This pin has an internal pull-up resistor.
0 = disable outputs, 1 = enable outputs.
©2018 Integrated Device Technology, Inc.
2
May 30, 2018
9FGV1004 Datasheet
Table 2. Pin Descriptions (Cont.)
Number
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Name
VDDDp
^OEB
OTP_VPP
OUT0#
OUT0
VDDO0
OUT1#
OUT1
VDDO1
OUT2#
OUT2
VDDO2
OUT3
OUT3#
VDDO3
VDDAp
Type
Power
Input
Power
Output
Output
Power
Output
Output
Power
Output
Output
Power
Output
Output
Power
Power
Description
Digital power. 1.8V to 3.3V. VDDAp and VDDDp should be connected to the same power
supply.
Active high input for enabling outputs. This pin has an internal pull-up resistor.
0 = disable outputs, 1 = enable outputs.
Voltage for programming OTP. During normal operation, this pin should be connected to the
same power rail as V
DDD
.
Complementary output clock 0.
Output clock 0.
Power supply for output 0.
Complementary output clock 1.
Output clock 1.
Power supply for output 1.
Complementary output clock 2.
Output clock 2.
Power supply for output 2.
Output clock 3.
Complementary output clock 3.
Power supply for output 3.
Power supply for analog circuits. VDDAp and VDDDp should be connected to the same
power supply. Programmable for nominally voltages of 1.8V, 2.5V or 3.3V.
23
vREF0_SEL_I2C#
Latched input/LVCMOS output. At power-up, the state of this pin is latched to select the
state of the I
2
C pins. After power-up, the pin acts as an LVCMOS reference output. This pin
Latched
has an internal pull-down.
I/O
1 = SEL0/SEL1.
0 = SCL/SDA.
Power
GND
Power supply for REF0 and REF1 and the internal XO. Programmable to 1.8V, 2.5V or 3.3V.
Connect to ground.
24
25
VDDREFp
EPAD
Note:
Unused outputs can be programmed off and left floating. V
DDREF
and V
DDO0
have to be connected.
©2018 Integrated Device Technology, Inc.
3
May 30, 2018
9FGV1004 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 9FGV1004 at absolute maximum ratings is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 3. Absolute Maximum Ratings
Parameter
Rating
Supply Voltage, V
DDA
, V
DDD
, V
DDO
Storage Temperature, T
STG
ESD Human Body Model
Junction Temperature
Inputs
XIN/CLKIN
Other Inputs
Outputs
Outputs, V
DDO
(LVCMOS)
Outputs, IO (SDA)
3.465V
-65°C to 150°C
2000V
125°C
0V to 1.2V voltage swing
-0.5V to V
DDD
-0.5V to V
DDO
+ 0.5V
10mA
Thermal Characteristics
Table 4. Thermal Characteristics
Parameter
Symbol
θ
JC
θ
Jb
Conditions
Junction to case
Junction to base
Junction to air, still air
Junction to air, 1 m/s air flow
Junction to air, 3 m/s air flow
Junction to air, 5 m/s air flow
Package
Typical Values
52
2.3
44
37
33
32
Units
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
1
1
1
1
1
1
Thermal Resistance
(devices with external crystal)
θ
JA0
θ
JA1
θ
JA3
θ
JA5
NBG24
1
EPAD soldered to board.
©2018 Integrated Device Technology, Inc.
4
May 30, 2018
9FGV1004 Datasheet
Recommended Operating Conditions
Table 5. Recommended Operating Conditions
Symbol
V
DDOx
V
DDD
V
DDA
T
A
C
L
t
PU
Parameter
Power supply voltage for supporting 1.8V outputs.
Power supply voltage for supporting 2.5V outputs.
Power supply voltage for supporting 3.3V outputs.
Power supply voltage for core logic functions.
Analog power supply voltage. Use filtered analog power supply if available.
Operating temperature, ambient.
Maximum load capacitance (3.3V LVCMOS only).
Power up time for all V
DD
s to reach minimum specified voltage (power
ramps must be monotonic).
Minimum
1.71
2.375
3.135
1.71
1.71
-40
Typical
1.8
2.5
3.3
Maximum Units
1.89
2.625
3.465
3.465
3.465
85
15
V
V
V
V
V
°C
pF
ms
0.05
5
Electrical Characteristics
V
DDx
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, T
A
= -40°C to +85°C unless stated otherwise.
Table 6. Common Electrical Characteristics
Parameter
Symbol
Conditions
Minimum
Typical
Maximum
Units
Notes
Input Frequency
f
IN
Crystal input frequency.
CLKIN input frequency.
Differential clock output
(LVDS/LP-HCSL).
8
1
10
10
10
2400
0.06
0.7 x V
DDD
GND - 0.3
0.65 x V
DDREF
-0.3
0.8
-0.3
25
50
240
325
200
156.25
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V
V
V
V
V
V
ns
pF
kΩ
1
5
Output Frequency
f
OUT
Single-ended clock output (LVCMOS).
Fractional or spread spectrum
configuration.
VCO Frequency
Loop Bandwidth
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input Rise/Fall Time
Input Capacitance
Internal Pull-up
Resistor
f
VCO
f
BW
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
T
R
/T
F
C
IN
R
UP
VCO operating frequency range.
Input frequency = 25MHz.
SEL[1:0].
SEL[1:0].
REF/SEL_I2C#.
REF/SEL_I2C#.
XIN/CLKIN.
XIN/CLKIN.
SEL1/SDA, SEL0/SCL.
SEL[1:0].
SEL[1:0] at 25°C.
2500
2600
0.9
V
DDD
+ 0.3
0.8
V
DDREF
+ 0.3
0.4
1.2
0.4
300
3
200
237
7
300
©2018 Integrated Device Technology, Inc.
5
May 30, 2018
RF/Wirelessly
京公网安备 11010802033920号
EEWORLD
