VersaClock
®
6E Programmable
Clock Generator
Description
The 5P49V6967 is a programmable clock generator intended for
high-performance consumer, networking, industrial, computing,
and data-communications applications. This is IDT’s sixth
generation of programmable clock technology (VersaClock 6E).
The frequencies are generated from a single reference clock. The
reference clock can originate from one of the two redundant clock
inputs. A glitchless manual switchover function allows one of the
redundant clocks to be selected during normal operation.
Two select pins allow up to four different configurations to be
programmed and may be used for different operating modes.
5P49V6967
Datasheet
Features
Typical Applications
Ethernet switch/router
PCI Express 1–4
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
Datacenter
Flexible 1.8V, 2.5V, 3.3V power rails
High-performance, low phase noise PLL, < 0.5ps RMS typical
phase jitter on outputs
Four banks of internal OTP memory
— In-system or factory programmable
I
2
C serial programming interface
— 0xD0 or 0xD4 I
2
C address options allow multiple devices
configured in a same system.
Reference LVCMOS output clock
Three Universal configurable outputs (OUT1, 2, 4):
— Differential (LVPECL, LVDS, or HCSL)
1kHz to 350MHz
— Two single-ended (in-phase or 180 degrees out of phase)
1kHz to 200MHz
— I/O VDDs can be mixed and matched, supporting 1.8V
(LVDS and LVCMOS), 2.5V, or 3.3V
— Independent spread spectrum on each output pair
Four additional LPHCSL outputs (OUT 3, 5, 6, 7)
— 1.8V low power supply
— 1kHz to 200MHz
Programmable output enable or power-down mode
Available in 5 × 5 mm 40-VFQFPN package
-40° to +85°C industrial temperature operation
Block Diagram
V
DDO
0
XIN/REF
XOUT
FOD1
OUT0_SEL_I2CB
V
DDO
1
OUT1
OUT1B
V
DDO
2
FOD2
PLL
OUT2
OUT2B
OEA
FOD3
OUT3, 5
OEB
OUT6, 7
V
DDO
4
FOD4
OUT4
OUT4B
SD/OE
SEL1/SDA
SEL0/SCL
V
DDA
V
DDD
OTP
and
Control
Logic
© 2018 Integrated Device Technology, Inc.
1
August 30, 2018
5P49V6967 Datasheet
Contents
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Pin Assignments ...........................................................................................................................................................................................3
Pin Descriptions............................................................................................................................................................................................3
Absolute Maximum Ratings ..........................................................................................................................................................................6
Thermal Characteristics................................................................................................................................................................................6
Recommended Operating Conditions ..........................................................................................................................................................6
Electrical Characteristics ..............................................................................................................................................................................7
Test Loads ..................................................................................................................................................................................................14
Jitter Performance Characteristics .............................................................................................................................................................15
PCI Express Jitter Performance and Specification .....................................................................................................................................16
Features and Functional Blocks .................................................................................................................................................................17
10.1 Device Startup and Power-on-Reset................................................................................................................................................17
10.2 Internal Crystal Oscillator (XIN/REF) ...............................................................................................................................................18
10.2.1 Choosing Crystals .............................................................................................................................................................18
10.2.2 Tuning the Crystal Load Capacitor....................................................................................................................................18
10.3 Programmable Loop Filter................................................................................................................................................................20
10.4 Fractional Output Dividers (FOD).....................................................................................................................................................20
10.4.1 Individual Spread Spectrum Modulation ...........................................................................................................................20
10.4.2 Bypass Mode ....................................................................................................................................................................20
10.4.3 Cascaded Mode ................................................................................................................................................................20
10.4.4 Dividers Alignment ............................................................................................................................................................20
10.4.5 Programmable Skew .........................................................................................................................................................21
10.5 Output Drivers ..................................................................................................................................................................................21
10.6 SD/OE Pin Function .........................................................................................................................................................................21
10.7 I
2
C Operation ...................................................................................................................................................................................22
Typical Application Circuit ..........................................................................................................................................................................23
11.1 Input – Driving the XIN/REF .............................................................................................................................................................24
11.1.1 Driving XIN/REF with a CMOS Driver ...............................................................................................................................24
11.1.2 Driving XIN with a LVPECL Driver ....................................................................................................................................25
11.2 Output – Single-ended or Differential Clock Terminations ...............................................................................................................26
11.2.1 LVDS Termination .............................................................................................................................................................26
11.2.2 LVPECL Termination ........................................................................................................................................................27
11.2.3 HCSL Termination.............................................................................................................................................................28
11.2.4 LVCMOS Termination .......................................................................................................................................................28
Package Outline Drawings .........................................................................................................................................................................29
Marking Diagram .........................................................................................................................................................................................29
Ordering Information ...................................................................................................................................................................................29
Revision History ..........................................................................................................................................................................................30
11.
12.
13.
14.
15.
© 2018 Integrated Device Technology, Inc.
2
August 30, 2018
5P49V6967 Datasheet
1.
Pin Assignments
Pin Assignments for 5
×
5 mm 40-VFQFPN Package – Top View
Figure 1.
OUT0_SEL_I2CB
OE_buffer
NC
XOUT
XIN/REF
V
DDA
V
DDO
OUT7
OUT7B
OUT6
OUT6B
SD/OE
1
2
3
4
5
40 39 38 37 36 35 34 33 32 31
30
29
28
27
OUT1
OUT1B
NC
OEB
V
DDO
0
V
DD
V
DDO
V
DDO
1
V
DDO
2
OUT2
OUT2B
V
DD
V
DD
V
DD_CORE
OUT3
OUT3B
NC
NC
EPAD
6
7
8
9
10
11 12 13 14 15 16
26
25
24
23
22
21
17 18 19 20
SEL0/SCL
SEL1/SD
V
DDO
OUT5B
40-pin VFQFPN
2.
Pin Descriptions
Pin Descriptions
Table 1.
Number
1
2
3
4
5
6
7
8
NC
XOUT
Name
Input
Input
Input
Power
Power
Output
Output
Output
Type
Do not connect
Crystal Oscillator interface output.
OUT4B
OUT5
V
DDO
4
OUT4
V
DD
OEA
Description
XIN/REF
VDDA
VDDO
OUT7
OUT7B
OUT6
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure
that the input voltage is 1.2V maximum.
Analog functions power supply pin. Connect to 1.8V.
Connect to 1.8V. Power pin for outputs 3, 5–7.
Output clock 7. Low-Power HCSL (LP-HCSL) output.
Complementary output clock 7. Low-power HCSL (LP-HCSL) output.
Output clock 6. Low-power HCSL (LP-HCSL) output.
© 2018 Integrated Device Technology, Inc.
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August 30, 2018
5P49V6967 Datasheet
Number
9
10
OUT6B
SD/OE
Name
Output
Input
Internal
Pull-down
Type
Description
Complementary output clock 6. Low-power HCSL (LP-HCSL) output.
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
controls the configuration of the SD/OE pin. The SH bit needs to be high for
SD/OE pin to be configured as SD. The SP bit (0x02) controls the polarity of the
signal to be either active HIGH or LOW only when pin is configured as OE
(Default is active LOW.) Weak internal pull down resistor. When configured as
SD, the device is shut down, differential outputs are driven high/low, and the
single-ended LVCMOS outputs are driven low. When configured as OE, and
outputs are disabled, the outputs can be selected to be tri-stated or driven
high/low.
Configuration select pin, or I
2
C SDA input as selected by OUT0_SEL_I2CB.
Configuration select pin, or I
2
C SCL input as selected by OUT0_SEL_I2CB.
Connect to 1.8V.
Connect to 1.8V. Power pin for outputs 3, 5–7.
Output clock 5. Low-power HCSL (LP-HCSL) output.
Complementary output clock 5. Low-power HCSL (LP-HCSL) output.
Internal
Pull-down
Active-low Output Enable pin for outputs 3 and 5.
0 = Enable outputs; 1 = Disable outputs. This pin has internal pull-down.
Connect to 1.8V to 3.3V. VDD supply for OUT4.
Output clock 4. For more information, see Output Drivers.
Complementary Output Clock 4. For more information, see Output Drivers.
Do not connect.
Do not connect.
Complementary Output Clock 3. Low-Power HCSL (LP-HCSL) output.
Output Clock 3. HCSL Low-Power HCSL (LP-HCSL) output.
Connect to 1.8V
Connect to 1.8V
Connect to 1.8V
Complementary Output Clock 2. For more information, see Output Drivers.
Output Clock 2. For more information, see Output Drivers.
Connect to 1.8V to 3.3V. VDD supply for OUT2.
Complementary Output Clock 1. For more information, see Output Drivers.
Output Clock 1. For more information, see Output Drivers.
Connect to 1.8V to 3.3V. VDD supply for OUT1.
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
SEL1/SDA
SEL0/SCL
VDD
VDDO
OUT5
OUT5B
OEA
VDDO4
OUT4
OUT4B
NC
NC
OUT3B
OUT3
VDD_Core
VDD
VDD
OUT2B
OUT2
VDDO2
OUT1B
OUT1
VDDO1
Input
Input
Power
Power
Output
Output
Input
Power
Output
Output
—
—
Output
Output
Power
Power
Power
Output
Output
Power
Output
Output
Power
Internal
Pull-down
Internal
Pull-down
© 2018 Integrated Device Technology, Inc.
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August 30, 2018
5P49V6967 Datasheet
Number
34
35
36
37
38
39
40
OEB
NC
VDDO
VDD
OE_buffer
VDDO0
OUT0_SE_I
2CB
Power
Output
Internal
Pull-down
Name
Input
—
Power
Power
Internal
Pull-up
Type
Internal
Pull-down
Description
Active-low Output Enable pin for outputs 6 and 7.
0 = Enable outputs; 1 = Disable outputs. This pin has internal pull-down.
Do not connect.
Connect to 1.8V. Power pin for outputs 3, 5–7.
Connect to 1.8V.
Active High Output enable for outputs 3, 5–7.
0 = Disable outputs; 1 = Enable outputs. This pin has internal pull-up.
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets the output
voltage levels for OUT0.
Latched input/LVCMOS output. At power up, the voltage at the pin
OUT0_SEL_I2CB is latched by the device and used to select the state of pins 11
and 12. If a weak pull-up (10Kohms) is placed on OUT0_SEL_I2CB, pins 11 and
12 will be configured as hardware select pins, SEL1 and SEL0. If a weak pull-
down (10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 11 and
12 will act as the SDA and SCL pins of an I
2
C interface. After power up, the pin
acts as a LVCMOS reference output.
Connect to ground pad.
ePAD
GND
GND
© 2018 Integrated Device Technology, Inc.
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August 30, 2018
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