HS9-4080AEH/PROTO datasheet, PDF

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HS9-4080AEH/PROTO: DescriptionDoor driver RADIATION HARDENED FULL BRIDGE DRIVER, PROTOTYPE, FP; Categorysemiconductor Power management IC Gate driver; File Size322KB，8 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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HS9-4080AEH/PROTO Overview

Door driver RADIATION HARDENED FULL BRIDGE DRIVER, PROTOTYPE, FP

HS9-4080AEH/PROTO Parametric

Parameter Name	Attribute value
Maker	Renesas Electronics Corporation
Product Category	gate driver
Shipping restrictions	This product may require additional documentation for export from the United States.
Installation style	SMD/SMT
Package/box	Flatpack-20
product	MOSFET Gate Drivers
Number of exciters	1 Driver
Rise Time	50 ns
Fall time	50 ns
Supply voltage - max.	18 V
Supply voltage - min.	12 V
Minimum operating temperature	- 55 C
Maximum operating temperature	+ 125 C
type	High Side, Low Side
series	HS-4080
Encapsulation	Tray
Number of outputs	1 Output
technology	Si
logical type	TTL
Factory packaging quantity	100

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DATASHEET

HS-4080AEH

Radiation Hardened Full Bridge N-Channel FET Driver

The

HS-4080AEH

is a monolithic, high frequency, medium

voltage Full Bridge N-Channel FET Driver IC. The device

includes a TTL-level input comparator, which can be used to

facilitate the “hysteresis” and PWM modes of operation. Its

HEN (High Enable) lead can force current to freewheel in the

bottom two external power MOSFETs, maintaining the upper

power MOSFETs off. The HS-4080AEH is well suited for use in

distributed DC power supplies and DC/DC converters, since it

can switch at high frequencies.

This device can also drive medium voltage motors and two

HS-4080AEHs can be used to drive high performance stepper

motors, since the short minimum “on-time” can provide fine

micro-stepping capability.

Short propagation delays maximize control loop crossover

frequencies and dead times, which can be adjusted to near

zero to minimize distortion, resulting in precise control of the

driven load.

Constructed with the Intersil dielectrically isolated radiation

hardened Silicon Gate (RSG) process, this device is immune to

single event latch-up and has been specifically designed to

provide highly reliable performance in harsh radiation

environments. Complete your design with radiation hardened

MOSFETs from Intersil.

Detailed Electrical Specifications for these devices are

contained in SMD

5962-99617.

FN4563

Rev 6.00

May 27, 2015

Features

• Electrically screened to SMD #

5962-99617

• QML qualified per MIL-PRF-38535 requirements

• Radiation environment

- Gamma dose . . . . . . . . . . . . . . . . . . . . . 300kRAD(Si) (max)

- Latch-up immune RSG DI process

• Drives N-Channel FET full bridge including high-side chop

capability

• Bootstrap supply max voltage to 95V

• TTL comparator input levels

• Drives 1000pF load with rise and fall times of 50ns

• User-programmable dead time

• Charge-pump and bootstrap maintain upper bias supplies

• DIS (Disable) pin pulls gates low

• Operates from single supply . . . . . . . . . . . . . . . . . . 12V to 18V

• Low power consumption

• Undervoltage protection

Applications

• Full bridge power supplies

• PWM motion control

Application Block Diagram

80V

12V

BHO

BHS

HEN

DIS

BLO

LOAD

HS-4080AEH

IN+

IN-

ALO

AHS

AHO

GND

FIGURE 1. APPLICATION BLOCK DIAGRAM

FN4563 Rev 6.00

May 27, 2015

Page 1 of 7

HS-4080AEH

Pin Descriptions

NUMBER

PIN NAME

BHB

DESCRIPTION

B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and

positive side of bootstrap capacitor to this pin. Internal charge pump supplies 50µA out of this pin to maintain bootstrap

supply. Internal circuitry clamps the bootstrap supply to approximately 15V.

High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers (Pins

11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can be driven by

signal levels of 0V to 18V (no greater than VDD). An internal 100µA pull-up to VDD will hold HEN high, so no connection is

required if high-side and low-side outputs are to be controlled by IN+/IN -inputs.

DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When

DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 18V (no

greater than VDD). An internal 100µA pull-up to VDD will hold DIS high if this pin is not driven.

Chip negative supply, generally will be ground.

OUTput of the input control comparator. This rail-to-rail output signal can be used for feedback and hysteresis.

Noninverting input of control comparator. This pin can only be driven by signal levels of 0V to 4.5V. If IN+ is greater than

IN- (Pin 7) then ALO and BHO are low level outputs and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO

and BHO are high level outputs and BLO and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control

for all outputs. HEN (Pin 2) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode,

dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9).

Inverting input of control comparator. This pin can only be driven by signal levels of 0V to 4.5V. See IN+ (Pin 6) description.

High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both

high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through

by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.

Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both

low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through

by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.

A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and

positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap

supply. Internal circuitry clamps the bootstrap supply to approximately 15V.

A High-side Output. Connect to gate of A High-side power MOSFET.

A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap

capacitor to this pin.

A Low-side Output. Connect to gate of A Low-side power MOSFET.

A Low-side Source connection. Connect to source of A Low-side power MOSFET.

Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes.

Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).

B Low-side Source connection. Connect to source of B Low-side power MOSFET.

B Low-side Output. Connect to gate of B Low-side power MOSFET.

B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap

capacitor to this pin.

B High-side Output. Connect to gate of B High-side power MOSFET.

HEN

DIS

VSS

OUT

IN+

IN-

HDEL

LDEL

AHB

AHO

AHS

ALO

ALS

VCC

VDD

BLS

BLO

BHS

BHO

FN4563 Rev 6.00

May 27, 2015

Page 3 of 7

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