EDBA164B2PR-1D-F-D datasheet, PDF

Datasheet> All Categories > storage> storage> EDBA164B2PR-1D-F-D

EDBA164B2PR-1D-F-D: DescriptionIC DRAM 16G PARALLEL 216FBGA; Categorystorage storage; File Size2MB，152 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

Download Datasheet Parametric View All

EDBA164B2PR-1D-F-D Overview

IC DRAM 16G PARALLEL 216FBGA

EDBA164B2PR-1D-F-D Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Micron Technology
package instruction	FBGA-216
Reach Compliance Code	compliant
access mode	DUAL BANK PAGE BURST
Other features	AUTO/SELF REFRESH; IT ALSO REQUIRES 1.8V NOMINAL SUPPLY
JESD-30 code	S-PBGA-B216
length	12 mm
memory density	17179869184 bit
Memory IC Type	DDR DRAM
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	216
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
organize	256MX64
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	SQUARE
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Maximum seat height	1 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.3 V
Minimum supply voltage (Vsup)	1.14 V
Nominal supply voltage (Vsup)	1.2 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	0.4 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	12 mm
Base Number Matches	1

Preview

Download Datasheet

View All

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

LPDDR2 SDRAM

EDB8164B4PR, EDB8164B4PK, EDB8164B4PT, EDBA164B2PR

Features

• Ultra-low-voltage core and I/O power supplies

• Frequency range

– 533 MHz (data rate: 1066 Mb/s/pin)

• 4n prefetch DDR architecture

• 8 internal banks for concurrent operation

• Multiplexed, double data rate, command/address

inputs; commands entered on each CK_t/CK_c

edge

• Bidirectional/differential data strobe per byte of

data (DQS_t/DQS_c)

• Programmable READ and WRITE latencies (RL/WL)

• Burst length: 4, 8, and 16

• Per-bank refresh for concurrent operation

• Auto temperature-compensated self refresh

(ATCSR) by built-in temperature sensor

• Partial-array self refresh (PASR)

• Deep power-down mode (DPD)

• Selectable output drive strength (DS)

• Clock-stop capability

• Lead-free (RoHS-compliant) and halogen-free

packaging

Table 1: Key Timing Parameters

Speed

Grade

Clock Rate Data Rate

(MHz)

(Mb/s/pin)

533

1066

Options

• Density/Page Size

– 8Gb/2-CS – dual die

– 16Gb/4-CS – quad die

• Organization

– x64

• V

DD1

DD2

DDQ

: 1.8V/1.2V/1.2V

• Revision

– Dual die

– Quad die

• FBGA “green” package

– 12mm x 12mm x 0.8mm, 216-ball

PoP FBGA package, dual die

– 12mm x 12mm x 0.8mm, 216-ball

PoP FBGA package, dual die

– 12mm x 12mm x 1.0mm, 216-ball

PoP FBGA package, quad die

– 14mm x 14mm x 0.7mm, 220-ball

PoP FBGA package, dual die

• Timing – cycle time

– 1.875ns @ RL = 8

• Special options

– Non-Automotive

• Operating temperature range

– From –30°C to +85°C

– From –40°C to +85°C

– From –40°C to +105°C

Marking

-1D

blank

Table 2: S4 Configuration Addressing

Architecture

Die configuration

Row addressing

Column addressing

Number of die

Die per rank

Ranks per channel

Note:

128 Meg x 64

16 Meg x 32 x 8 banks x 2 channel

16K A[13:0]

1K A[9:0]

256 Meg x 64

32 Meg x 32 x 8 banks x 2 channel

16K A[13:0]

1K A[9:0]

1. A channel is a complete LPDRAM interface, including command/address and data pins.

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

Contents

LPDDR2 Array Configuration ............................................................................................................................ 9

General Notes .............................................................................................................................................. 9

Specifications ........................................................................................................................................... 10

Package Block Diagrams ................................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 18

Ball Assignments ............................................................................................................................................ 21

Ball Descriptions ............................................................................................................................................ 24

Functional Description ................................................................................................................................... 25

Simplified State Diagram ................................................................................................................................ 26

Power-Up and Initialization ............................................................................................................................ 28

Voltage Ramp and Device Initialization ....................................................................................................... 28

Initialization After RESET (Without Voltage Ramp) ...................................................................................... 30

Power-Off Sequence ....................................................................................................................................... 30

Uncontrolled Power-Off Sequence .............................................................................................................. 31

Mode Register Definition ................................................................................................................................ 31

Mode Register Assignments and Definitions ................................................................................................ 31

Commands and Timing .................................................................................................................................. 42

ACTIVATE Command ..................................................................................................................................... 43

8-Bank Device Operation ............................................................................................................................ 44

Read and Write Access Modes ......................................................................................................................... 45

Burst READ Command ................................................................................................................................... 45

READs Interrupted by a READ ..................................................................................................................... 52

Burst WRITE Command .................................................................................................................................. 52

WRITEs Interrupted by a WRITE ................................................................................................................. 55

BURST TERMINATE Command ...................................................................................................................... 55

Write Data Mask ............................................................................................................................................. 57

PRECHARGE Command ................................................................................................................................. 58

READ Burst Followed by PRECHARGE ......................................................................................................... 59

WRITE Burst Followed by PRECHARGE ....................................................................................................... 60

Auto Precharge operation ........................................................................................................................... 61

READ Burst with Auto Precharge ................................................................................................................. 61

WRITE Burst with Auto Precharge ............................................................................................................... 62

REFRESH Command ...................................................................................................................................... 64

REFRESH Requirements ............................................................................................................................. 66

SELF REFRESH Operation ............................................................................................................................... 73

Partial-Array Self Refresh – Bank Masking .................................................................................................... 75

Partial-Array Self Refresh – Segment Masking .............................................................................................. 75

MODE REGISTER READ ................................................................................................................................. 76

Temperature Sensor ................................................................................................................................... 78

DQ Calibration ........................................................................................................................................... 80

MODE REGISTER WRITE Command ............................................................................................................... 82

MRW RESET Command .............................................................................................................................. 82

MRW ZQ Calibration Commands ................................................................................................................ 83

ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 85

Power-Down .................................................................................................................................................. 85

Deep Power-Down ......................................................................................................................................... 92

Input Clock Frequency Changes and Stop Events ............................................................................................. 93

Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 93

Input Clock Frequency Changes and Clock Stop with CKE HIGH .................................................................. 94

NO OPERATION Command ............................................................................................................................ 94

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

Truth Tables ................................................................................................................................................... 94

Absolute Maximum Ratings ........................................................................................................................... 102

Input/Output Capacitance ............................................................................................................................. 102

Electrical Specifications – I

Specifications and Conditions ........................................................................... 103

AC and DC Operating Conditions ................................................................................................................... 106

AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 107

REF

Tolerances ......................................................................................................................................... 108

Input Signal .............................................................................................................................................. 110

AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 112

Single-Ended Requirements for Differential Signals .................................................................................... 113

Differential Input Crosspoint Voltage ......................................................................................................... 115

Input Slew Rate ......................................................................................................................................... 116

Output Characteristics and Operating Conditions ........................................................................................... 116

Single-Ended Output Slew Rate .................................................................................................................. 117

Differential Output Slew Rate ..................................................................................................................... 118

HSUL_12 Driver Output Timing Reference Load ......................................................................................... 120

Output Driver Impedance .............................................................................................................................. 121

Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 122

Output Driver Temperature and Voltage Sensitivity ..................................................................................... 123

Output Impedance Characteristics Without ZQ Calibration ......................................................................... 123

Clock Specification ........................................................................................................................................ 126

CK(abs),

CH(abs), and

CL(abs) ................................................................................................................ 128

Clock Period Jitter .......................................................................................................................................... 128

Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 128

Cycle Time Derating for Core Timing Parameters ........................................................................................ 129

Clock Cycle Derating for Core Timing Parameters ....................................................................................... 129

Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 129

Clock Jitter Effects on READ Timing Parameters .......................................................................................... 129

Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 130

Refresh Requirements Parameters .................................................................................................................. 131

AC Timing ..................................................................................................................................................... 131

CA and CS_n Setup, Hold, and Derating .......................................................................................................... 137

Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 145

Revision History ............................................................................................................................................ 152

Rev. F – 08/16 ............................................................................................................................................ 152

Rev. E – 05/16 ............................................................................................................................................ 152

Rev. D – 03/16 ............................................................................................................................................ 152

Rev. C – 02/16 ............................................................................................................................................ 152

Rev. B – 01/15 ............................................................................................................................................ 152

Rev. A – 09/14 ............................................................................................................................................ 152

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

List of Figures

Figure 1: LPDDR2 Part Numbering ................................................................................................................... 2

Figure 2: Dual Die Single Rank, Dual Channel Package Block Diagram ............................................................. 16

Figure 3: Quad Die Dual Rank, Dual Channel Package Block Diagram ............................................................. 17

Figure 4: 216-Ball FBGA (12mm x 12mm x 0.8mm) – EDB8164B4PR, EDB8164B4PT ......................................... 18

Figure 5: 216-Ball FBGA (12mm x 12mm x 1.0mm) – EDBA164B2PR ................................................................ 19

Figure 6: 220-Ball FBGA (14mm x 14mm x 0.7mm) – EDB8164B4PK ................................................................ 20

Figure 7: 216-Ball Dual-Channel FBGA – 2 x 4Gb Die ...................................................................................... 21

Figure 8: 220-Ball Dual-Channel FBGA – 2 x 4Gb Die ...................................................................................... 22

Figure 9: 216-Ball Dual-Channel FBGA – 4 x 4Gb Die ...................................................................................... 23

Figure 10: Functional Block Diagram ............................................................................................................. 26

Figure 11: Simplified State Diagram ............................................................................................................... 27

Figure 12: Voltage Ramp and Initialization Sequence ...................................................................................... 30

Figure 13: Command and Input Setup and Hold ............................................................................................. 43

Figure 14: CKE Input Setup and Hold ............................................................................................................. 43

Figure 15: ACTIVATE Command .................................................................................................................... 44

Figure 16:

FAW Timing (8-Bank Devices) ....................................................................................................... 45

Figure 17: READ Output Timing –

DQSCK (MAX) ........................................................................................... 46

Figure 18: READ Output Timing –

DQSCK (MIN) ........................................................................................... 46

Figure 19: Burst READ – RL = 5, BL = 4,

DQSCK >

CK ..................................................................................... 47

Figure 20: Burst READ – RL = 3, BL = 8,

DQSCK <

CK ..................................................................................... 47

Figure 21:

DQSCKDL Timing ........................................................................................................................ 48

Figure 22:

DQSCKDM Timing ....................................................................................................................... 49

Figure 23:

DQSCKDS Timing ......................................................................................................................... 50

Figure 24: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 51

Figure 25: Seamless Burst READ – RL = 3, BL = 4,

CCD = 2 .............................................................................. 51

Figure 26: READ Burst Interrupt Example – RL = 3, BL = 8,

CCD = 2 ................................................................. 52

Figure 27: Data Input (WRITE) Timing ........................................................................................................... 53

Figure 28: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 53

Figure 29: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 54

Figure 30: Seamless Burst WRITE – WL = 1, BL = 4,

CCD = 2 ............................................................................ 54

Figure 31: WRITE Burst Interrupt Timing – WL = 1, BL = 8,

CCD = 2 ................................................................ 55

Figure 32: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 56

Figure 33: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 57

Figure 34: Data Mask Timing ......................................................................................................................... 57

Figure 35: Write Data Mask – Second Data Bit Masked .................................................................................... 58

Figure 36: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(

RTP(MIN)/

CK) = 2 ................................ 59

Figure 37: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(

RTP(MIN)/

CK) = 3 ................................ 60

Figure 38: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 61

Figure 39: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(

RTP(MIN)/

CK) = 2 ........................................ 62

Figure 40: WRITE Burst with Auto Precharge – WL = 1, BL = 4 .......................................................................... 63

Figure 41:

SRF Definition .............................................................................................................................. 67

Figure 42: Regular Distributed Refresh Pattern ............................................................................................... 69

Figure 43: Supported Transition from Repetitive REFRESH Burst .................................................................... 70

Figure 44: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 71

Figure 45: Recommended Self Refresh Entry and Exit ..................................................................................... 72

Figure 46: All-Bank REFRESH Operation ........................................................................................................ 73

Figure 47: Per-Bank REFRESH Operation ....................................................................................................... 73

Figure 48: SELF REFRESH Operation .............................................................................................................. 74

Figure 49: MRR Timing – RL = 3,

MRR = 2 ...................................................................................................... 76

Figure 50: READ to MRR Timing – RL = 3,

MRR = 2 ......................................................................................... 77

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Recommended Resources

Circular chasing colored light circuit

Remote control light switch circuit

Presettable analog timer circuit diagram

Nanosecond pulse detection circuit

Principle and application of numerically controlled gain programming instrument amplifier PGA202/203

Triangular multi-branch parallel three-phase motor winding open circuit inspection circuit

(A-Current Signal Detection Device) Tianjin First Prize_Topic A: [size=6][font=微软雅黑, "]Abstract: [/font][/size][p=30, 2, left][font=微软雅黑, "][size=14px]This current signal detection device can amplify the signal generated by the arbitrary waveform signal generator u...; sigma Electronics Design Contest

2. Use and simulation of common XILINX IP CORE: ...; 至芯科技FPGA大牛 FPGA/CPLD

What does a digital design engineer mainly do? How do you get started? What does a digital verification engineer mainly do? How do you do it?: What does a digital design engineer mainly do? How do you get started? What does a digital verification engineer mainly do? How do you do it? It is said that digital design engineers are more hardware...; 851779592 Domestic Chip Exchange

3. Lighting Case and Extension: This is my third review. Many experts in the forum have written great review posts. I can only proceed step by step at my own pace. Review post 1 "Unboxing Review": https://en.eeworld.com/bbs/thread-1...; sonicfirr GD32 MCU

CH549EVT development board test - unpacking and development platform establishment: First of all, I would like to thank Qinheng Electronics and EEWORLD for providing this review opportunity!1. UnboxingThe picture below is the CH549EVT-L development board evaluated in this review, whi...; hujj MCU

EEWORLD University ---- Intel SoC FPGA Development and Application Training Course by Xiaomei: Intel SoC FPGA Development and Application Training Course by Xiaomei : https://training.eeworld.com.cn/course/5037What is SoC FPGA, what are its advantages, and how to use SoC FPGA for development? I...; 抛砖引玉 Talking

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components