SN74ACT32PWE4 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> SN74ACT32PWE4

SN74ACT32PWE4: DescriptionLogic Gates Quadruple 2-Input Positive-OR Gates; Categorylogic logic; File Size350KB，12 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

Stay tuned Parametric Compare

SN74ACT32PWE4 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	SN74ACT32PWE4	-	-	View	Buy Now

SN74ACT32PWE4 Overview

Logic Gates Quadruple 2-Input Positive-OR Gates

SN74ACT32PWE4 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP14,.25
Contacts	14
Reach Compliance Code	unknow
series	ACT
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	OR GATE
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Prop。Delay @ Nom-Su	10 ns
propagation delay (tpd)	10 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm

SN74ACT32PWE4 Related Products

	SN74ACT32PWE4	SN74ACT32PWRE4	SN74ACT32NSRE4	SN74ACT32DE4	SN74ACT32DBRE4
Description	Logic Gates Quadruple 2-Input Positive-OR Gates	Logic Gates Quadruple 2-Input Positive-OR Gates	Logic Gates Quadruple 2-Input Positive-OR Gates	Logic Gates Quadruple 2-Input Positive-OR Gates	Logic Gates Quadruple 2-Input Positive-OR Gates
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Parts packaging code	TSSOP	TSSOP	SOIC	SOIC	SSOP
package instruction	TSSOP, TSSOP14,.25	TSSOP, TSSOP14,.25	SOP, SOP14,.3	SOP, SOP14,.25	SOP, SSOP14,.3
Contacts	14	14	14	14	14
Reach Compliance Code	unknow	unknow	unknow	unknow	unknow
series	ACT	ACT	ACT	ACT	ACT
JESD-30 code	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e4	e4	e4	e4	e4
length	5 mm	5 mm	10.2 mm	8.65 mm	8.65 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	OR GATE	OR GATE	OR GATE	OR GATE	OR GATE
MaximumI(ol)	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A
Humidity sensitivity level	1	1	1	1	1
Number of functions	4	4	4	4	4
Number of entries	2	2	2	2	2
Number of terminals	14	14	14	14	14
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	SOP	SOP	SOP
Encapsulate equivalent code	TSSOP14,.25	TSSOP14,.25	SOP14,.3	SOP14,.25	SSOP14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260	260	260	260	260
power supply	5 V	5 V	5 V	5 V	5 V
Prop。Delay @ Nom-Su	10 ns	10 ns	10 ns	10 ns	10 ns
propagation delay (tpd)	10 ns	10 ns	10 ns	10 ns	10 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO	NO
Maximum seat height	1.2 mm	1.2 mm	2 mm	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	4.4 mm	4.4 mm	5.3 mm	3.9 mm	3.9 mm
Maker	Texas Instruments	-	Texas Instruments	Texas Instruments	Texas Instruments
method of packing	-	TAPE AND REEL	TAPE AND REEL	TUBE	TAPE AND REEL

Recommended Resources

Equivalent circuit of treble attenuation

Non-two-wire sound and light control stair delay switch circuit (5)

High sensitivity field strength meter circuit diagram

Basic application standard application circuit diagram of the MAX736 series

Hitachi F1 movement power circuit

Computer motherboard circuit diagram 820 2_11

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components