16-Channel, 16-/14-Bit,
Serial Input, Voltage-Output DAC
AD5360/AD5361
FEATURES
16-channel DAC in 52-lead LQFP and 56-lead LFCSP
packages
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of −10 V to +10 V
Multiple output spans available
Temperature monitoring function
Channel monitoring multiplexer
GPIO function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI-compatible serial interface
2.5 V to 5.5 V digital interface
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Instrumentation
Industrial control systems
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical line cards
FUNCTIONAL BLOCK DIAGRAM
DV
CC
V
DD
V
SS
AGND DGND
LDAC
TEMP_OUT
PEC
MON_IN0
MON_IN1
TEMP
SENSOR
8
CONTROL
REGISTER
VOUT0 TO
VOUT15
6
MUX
MON_OUT
GPIO
BIN/2SCOMP
SYNC
SDI
SCLK
SDO
BUSY
8
RESET
CLR
STATE
MACHINE
n
n
n
n
A/B SELECT
REGISTER
X1 REGISTER
n
M REGISTER
C REGISTER
n
8
n
TO
MUX 2s
n
A/B
MUX
X2A REGISTER
X2B REGISTER
MUX
2
n
14
OFS1
REGISTER
n
OFFSET
DAC 1
BUFFER
DAC 0
REGISTER
n
DAC 0
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
SERIAL
INTERFACE
n
n
n
GPIO
REGISTER
2
n
n
n
n = 16 FOR AD5360
n = 14 FOR AD5361
8
A/B SELECT
REGISTER
X1 REGISTER
n
M REGISTER
C REGISTER
n
8
n
TO
MUX 2s
n
A/B
MUX
X2A REGISTER
X2B REGISTER
MUX
2
n
VREF0
14
OFS0
REGISTER
14
OFFSET
DAC 0
BUFFER
BUFFER
GROUP 0
n
DAC 0
REGISTER
DAC 0
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND0
VREF1
·
·
·
·
·
·
n
n
·
·
·
·
·
·
n
·
·
·
·
·
·
n
·
·
·
·
·
·
A/B
MUX
X1 REGISTER
M REGISTER
C REGISTER
X2A REGISTER
X2B REGISTER
·
·
·
·
·
MUX n
2
·
·
·
·
·
n
DAC 7
REGISTER
·
·
·
·
·
·
·
·
·
·
·
·
DAC 7
·
·
·
·
·
·
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
GROUP 1
·
·
·
·
·
·
n
n
n
·
·
·
·
·
·
n
·
·
·
·
·
·
n
·
·
·
·
·
·
A/B
MUX
AD5360/
AD5361
X1 REGISTER
M REGISTER
C REGISTER
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
MUX n
2
·
·
·
·
·
·
n
DAC 7
REGISTER
·
·
·
·
·
·
·
·
·
·
·
DAC 7
·
·
·
·
·
·
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
n
n
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved.
05761-007
AD5360/AD5361
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 14
Functional Description .................................................................. 15
DAC Architecture ....................................................................... 15
Channel Groups .......................................................................... 15
A/B Registers Gain/Offset Adjustment ................................... 16
Offset DACs ................................................................................ 16
Output Amplifier ........................................................................ 17
Transfer Function ....................................................................... 17
Reference Selection .................................................................... 17
Calibration ................................................................................... 18
Reset Function ............................................................................ 19
Clear Function ............................................................................ 19
BUSY and LDAC Functions...................................................... 19
BIN/2SCOMP PIN ..................................................................... 19
Temperature Sensor ................................................................... 19
Monitor Function ....................................................................... 20
GPIO Pin ..................................................................................... 20
Power-Down Mode .................................................................... 20
Thermal Monitoring Function ................................................. 20
Toggle Mode................................................................................ 20
Serial Interface ................................................................................ 21
SPI Write Mode .......................................................................... 21
SPI Readback Mode ................................................................... 22
Register Update Rates ................................................................ 22
Packet Error Checking ............................................................... 22
Channel Addressing and Special Modes ................................. 23
Special Function Mode .............................................................. 24
Power Supply Decoupling ......................................................... 25
Power Supply Sequencing ......................................................... 25
Interfacing Examples...................................................................... 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
2/08—Rev. 0 to Rev. A
Added LFCSP Package ....................................................... Universal
Change to DC Crosstalk Parameter ............................................... 4
Change to Power Dissipation Unloaded (P) Parameter .............. 5
Added t
23
Parameter ......................................................................... 6
Change to Figure 4 ........................................................................... 7
Change to Table 5 Summary ........................................................... 9
Added Figure 8 ................................................................................ 10
Changes to Table 6 .......................................................................... 10
Changes to Calibration Section .................................................... 18
Changes to Reset Function Section .............................................. 19
Added Packet Error Checking Section ........................................ 22
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
10/07—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD5360/AD5361
GENERAL DESCRIPTION
The AD5360/AD5361 contain sixteen, 16-/14-bit DACs in a
single 52-lead LQFP or 56-lead LFCSP package. They provide
buffered voltage outputs with a span four times the reference
voltage. The gain and offset of each DAC can be independently
trimmed to remove errors. For even greater flexibility, the device is
divided into two groups of eight DACs, and the output range of
each group can be independently adjusted by an offset DAC.
The AD5360/AD5361 offer guaranteed operation over a wide
supply range with V
SS
from −4.5 V to −16.5 V and V
DD
from
+8 V to +16.5 V. The output amplifier headroom requirement
is 1.4 V.
The AD5360/AD5361 have a high speed 4-wire serial interface,
which is compatible with SPI, QSPI™, MICROWIRE™, and DSP
interface standards and can handle clock speeds of up to
50 MHz. All the outputs can be updated simultaneously by
taking the LDAC input low. Each channel has a programmable
gain register and an offset adjust register.
Each DAC output is amplified and buffered on-chip with
respect to an external SIGGNDx input. The DAC outputs can
also be switched to SIGGNDx via the CLR pin.
Rev. A | Page 3 of 28
AD5360/AD5361
SPECIFICATIONS
DV
CC
= 2.5 V to 5.5 V; V
DD
= 9 V to 16.5 V; V
SS
= −16.5 V to −4.5 V; V
REF
= 5 V; AGND = DGND = SIGGND = 0 V; R
L
= open circuit;
gain (M), offset (C), and DAC offset registers at default value; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
ACCURACY
Resolution
AD5360
AD5361
Relative Accuracy
AD5360
AD5361
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
Zero-Scale Error
2
Full-Scale Error
2
Span Error of Offset DAC
VOUTx
3
Temperature Coefficient
DC Crosstalk
4
REFERENCE INPUTS (VREF0, VREF1)
2
VREF Input Current
VREF Range
2
SIGGND INPUT (SIGGND0 to SIGGND1)
4
DC Input Impedance
Input Range
SIGGND Gain
OUTPUT CHARACTERISTICS
2
Output Voltage Range
Nominal Output Voltage Range
Short-Circuit Current
Load Current
Capacitive Load
DC Output Impedance
MONITOR PIN (MON_OUT)
4
Output Impedance
DAC Output at Positive Full-Scale
DAC Output at Negative Full-Scale
Three-State Leakage Current
Continuous Current Limit
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
4
B Version
1
Unit
Test Conditions/Comments
16
14
±4
±1
±1
±15
±20
0.1
1
1
±75
5
180
Bits
Bits
LSB max
LSB max
LSB max
mV max
mV max
% FSR
LSB typ
LSB typ
mV max
ppm FSR/°C typ
μV max
Guaranteed monotonic by design over temperature
Before calibration
Before calibration
Before calibration
After calibration
After calibration
See the
Offset DACS
section for details
Includes linearity, offset, and gain drift
Typically 20 μV; measured channel at midscale, full-scale
change on any other channel
Per input; typically ±30 nA
±2% for specified operation
Typically 55 kΩ
±10
2/5
50
±0.5
0.995/1.005
V
SS
+ 1.4
V
DD
− 1.4
−10 to +10
15
±1
2200
0.5
μA max
V min/max
kΩ min
V max
Min/max
V min
V max
V nominal
mA max
mA max
pF max
Ω max
I
LOAD
= 1 mA
I
LOAD
= 1 mA
VOUTx
3
to DV
CC
, V
DD
, or V
SS
1000
500
100
2
1.7
2.0
0.8
±1
±20
10
Ω typ
Ω typ
nA typ
mA max
V min
V min
V max
μA max
μA max
pF max
JEDEC compliant
DV
CC
= 2.5 V to 3.6 V
DV
CC
= 3.6 V to 5.5 V
DV
CC
= 2.5 V to 5.5 V
RESET, SYNC, SDI, and SCLK pins
CLR, BIN/2SCOMP, and GPIO pins
Rev. A | Page 4 of 28
AD5360/AD5361
Parameter
DIGITAL OUTPUTS (SDO, BUSY, GPIO, PEC)
Output Low Voltage
Output High Voltage (SDO)
High Impedance Leakage Current
High Impedance Output Capacitance
4
TEMPERATURE SENSOR (TEMP_OUT)
4
Accuracy
Output Voltage at 25°C
Output Voltage Scale Factor
Output Load Current
Power-On Time
POWER REQUIREMENTS
DV
CC
V
DD
V
SS
Power Supply Sensitivity
4
∆ Full Scale/∆ V
DD
∆ Full Scale/∆ V
SS
∆ Full Scale/∆ DV
CC
DI
CC
I
DD
I
SS
Power-Down Mode
DI
CC
I
DD
I
SS
Power Dissipation
Power Dissipation Unloaded (P)
Junction Temperature
1
2
B Version
1
0.5
DV
CC
− 0.5
±5
10
±1
±5
1.46
4.4
200
10
2.5/5.5
8/16.5
−4.5/−16.5
−75
−75
−90
2
10
10
5
35
−35
245
130
Unit
V max
V min
μA max
pF typ
°C typ
°C typ
V typ
mV/°C typ
μA max
ms typ
V min/max
V min/max
V min/max
dB typ
dB typ
dB typ
mA max
mA max
mA max
μA typ
μA typ
μA typ
mW max
°C max
Test Conditions/Comments
Sinking 200 μA
Sourcing 200 μA
SDO only
@ 25°C
−40°C < T < +85°C
Current source only
To within ±5°C
V
CC
= 5.5 V, V
IH
= DV
CC
, V
IL
= GND
Outputs unloaded
Outputs unloaded
Bit 0 in the Control Register is 1
V
SS
= −12 V, V
DD
= +12 V, DV
CC
= 2.5 V
T
J
= T
A
+ P
TOTAL
× θ
JA
Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.
Specifications are guaranteed for a 5 V reference only.
3
VOUTx refers to any of VOUT0 to VOUT15.
4
Guaranteed by design and characterization, not production tested.
AC CHARACTERISTICS
DV
CC
= 2.5 V; V
DD
= 15 V; V
SS
= −15 V; V
REF
= 5 V; AGND = DGND = SIGGND = 0 V; C
L
= 200 pF; R
L
= 10 kΩ; gain (M), offset (C), and
DAC offset registers at default value; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
1
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 10 kHz
1
B Version
1
20
30
1
5
10
100
10
0.2
0.02
250
Unit
μs typ
μs max
V/μs typ
nV-s typ
mV max
dB typ
nV-s typ
nV-s typ
nV-s typ
nV/√Hz typ
Test Conditions/Comments
Full-scale change
DAC latch contents alternately loaded with all 0s and all 1s
VREF0, VREF1 = 2 V p-p, 1 kHz
Effect of input bus activity on DAC output under test
VREF0 = VREF1 = 0 V
Guaranteed by design and characterization, not production tested.
Rev. A | Page 5 of 28
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