AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVED16F664LSD8TS-XX
16M X 64 DRAM SODIMM, EDO MODE, Using 8M X 8 Stacked, 4K Refresh, 3.3V
DESCRIPTION
The AVED Memory Products AVED16F664LSD8TS-XX is a
16M bit X 64 Dynamic RAM high density memory module.
The AVED Memory Products AVED16F664LSD8TS-XX
consists of sixteen CMOS 8M X 8 bit (stacked) DRAMs in
TSOP 400mil packages and a 2K EEPROM in 8-pin TSSOP
package mounted on a 144-pin glass-epoxy substrate. A 0.1
or 0.01uF decoupling capacitor is mounted on the printed
circuit board for each DRAM. The AVED Memory Products
AVED16F664LSD8TS-XX is a Dual in-line Memory Module
and is intended for mounting into 144-pin edge connector
sockets.
APPLICATION
Main Memory unit for computer, Microcomputer memory,
Refresh memory for CRT.
FEATURES
•
Performance Ranges
Speed
-5
-6
tRAC
50ns
60ns
tCAC
13ns
15ns
tHPC
20ns
25ns
PIN NAMES
Pin Name
A0 - A11
DQ0 - DQ63
W0 - W2
OE0 - OE2
RAS0 - RAS3
CAS0 - CAS7
Vcc
Vss
SDA
SCL
SA0 - SA2
Function
Address Inputs
Data In/Out
Read/Write Enable
Output Enable
Row Address Strobe
Colmn Address Strobe
Power (+3.3V)
Ground
Serial PD/Data I/O
Serial PD Clock Input
Serial PD Address Input
• PART IDENTIFICATION
- AVED16F664LSD8TS-XX
4K cycles/64ms, TSOP
- (XX= -5, -6)
•
•
•
•
•
•
•
•
Extended Data Out Mode Operation
New JEDEC standard proposal with EEPROM
Serial Presence Detect with EEPROM
CAS before RAS refresh capability
Self-refresh capability
RAS-only and Hidden refresh capability
LVTTL compatible inputs and outputs
Single +3.3V ± 0.3V power supply
Revision: A
Revision Date: 1/2000
Document number: 44605
page number: 1 of 7
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVED16F664LSD8TS-XX
16M X 64 DRAM SODIMM, EDO MODE, Using 8M X 8 Stacked, 4K Refresh, 3.3V
PIN CONFIGURATIONS (FRONT SIDE / BACK SIDE)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
Front
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
Vss
CAS0
CAS1
Vcc
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ12
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
Back
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
CAS4
CAS5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
Pin
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
Front
DQ13
DQ14
DQ15
Vss
NC
NC
NC
Vcc
NC
W
RAS0
RAS1
OE
Vss
NC
NC
Vcc
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
Pin
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
Back
DQ45
DQ46
DQ47
Vss
NC
NC
NC
Vcc
NC
NC
NC
NC
NC
Vss
NC
NC
Vcc
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
Pin
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Front
DQ22
DQ23
Vcc
A6
A8
Vss
A9
A10
Vcc
CAS2
CAS3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
Pin
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Back
DQ54
DQ55
Vcc
A7
A11
Vss
A12
NC
Vcc
CAS6
CAS7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vcc
Revision: A
Revision Date: 1/2000
Document number: 44605
page number: 2 of 7
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVED16F664LSD8TS-XX
16M X 64 DRAM SODIMM, EDO MODE, Using 8M X 8 Stacked, 4K Refresh, 3.3V
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Storage Temperature
Power Dissipation
Short Circuit Output Current
*
Symbol
V
IN
, VOUT
Vcc
Tstg
Pd
IOS
Rating
-0.5 to + 4.6
-0.5 to + 4.6
-55 to + 125
8
50
Unit
V
V
ºC
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, Ta = 0 to 70ºC)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
Vcc
Vss
V
IH
V
IL
Min
3.0
0
2.0
- 0.3**
Typ
3.3
0
-
-
Max
3.6
0
Vcc+0.3*
0.8
Unit
V
V
V
V
*1: Vcc+ 1.3V/15ns, Pulse width is measured at Vcc.
**2: -1.3V/15ns, Pulse width is measured at Vss.
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
AVED16F664LSD8TS-XX
Symbol
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
ICC8
I
I(L)
I
0(L)
V
OH
V
OL
ICC1:
ICC2:
ICC3:
ICC4:
ICC5:
ICC6:
ICC7:
Speed
-5
-6
-
-5
-6
-5
-6
-
-5
-6
-
-
-
-
-
-
Min
-
-
-
-
-
-
-
-
-
-
-
-
-16
-2
2.4
-
Max
1568
1408
16
1568
1408
1248
1088
8
1568
1408
11.2
11.2
16
2
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
Operating Current * (
RAS
,
CAS
,
Address cycling @tRC=min.)
Standby Current (
RAS
=
CAS
=
W
= V
IH
)
RAS
Only Refresh Current * (
CAS
= V
IH
,
RAS
cycling @tRC = min.)
EDO Mode Current * (
RAS
=V
IL
,
CAS
address cycling: tHPC=min.)
Standby Current (
RAS
=
CAS
=
W
=Vcc-0.2V)
CAS
-Before-
RAS
Refresh Current * (
RAS
and
CAS
cycling @ tRC = min.)
Battery back-up current. Average power supply, Battery back-up mode.
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, CAS=0.2V.
t
RC
=31.25us,
t
RAS
=
t
RAS
min~300ns.
ICCS:
I1(L):
I0(L):
V
OH
:
V
OL
:
Self-Refresh Current, RAS=CAS=V
IL
, W=OE=A0-A11=Vcc-0.2V or 0.2V,DQ-DQ63=Vcc-0.2V or Open
Input Leakage Current (Any input 0
£
V
IN
£
Vcc+0.3V, all other pins not under test = 0V.)
NOTE: ICC1,ICC3,ICC4 and ICC6 are dependent on output loading and cycle rates.
Output Leakage Current (Data out is disabled, 0V
£
Vout
£
Vcc)
Specified values are obtained with the output open. ICC is specified as an
average current. In ICC1, ICC3 and ICC6 address can be changed maximum
Output High Voltage Level (I
OH
= -2mA)
once while RAS = VIL. In ICC4, address can be changed maximum once
Output Low Voltage Level (I
OL
= 2mA)
within one EDO mode cycle, tHPC.
Revision: A
Revision Date: 1/2000
Document number: 44605
page number: 3 of 7
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVED16F664LSD8TS-XX
16M X 64 DRAM SODIMM, EDO MODE, Using 8M X 8 Stacked, 4K Refresh, 3.3V
CAPACITANCE
(Ta = 0 - 70
ºC,
f=1MHz)
Item
Input capacitance [A0 - A11]
Input capacitance [WE0 - WE2, OE0 - OE2]
Input capacitance
[
RAS0 -RAS3
]
Input capacitance [CAS0 - CAS7
]
Input/Output capacitance [DQ0 - 63]
Symbol
CIN1
CIN2
CIN3
CIN4
CDQ
Min
-
-
-
-
-
Max
95
70
40
24
18
Unit
pF
pF
pF
pF
pF
AC CHARACTERISTICS
(0ºC
£
Ta
£
70ºC, Vcc=3.3V
±
0.3V, V
SS
=OV
-50
STAND OPERATION
ANDARD
STANDARD OPERATION
Random read or write cycle time
Read-modify-write cycle time
Access time from
RAS
Access time from
CAS
Access time from column address
CAS
to output in Low-Z
Test condition: Vih/Vil=2.2/0.7V, Voh/Vol=2.0V/0.8V, Output loading CL = 100pF
- 60
Max
Min
110
140
50
13
25
60
15
30
0
10
50
10K
0
2
40
60
15
55
10K
37
25
10
20
15
5
10
0
10
0
10
50
30
0
0
0
0
10
10
45
10K
45
30
10K
15
50
Symbol
tRC
tRWC
tRAC
tCAC
tAA
tCLZ
tCEZ
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tCP
tASR
tRAH
tASC
tCAH
tAR
tRAL
tRCS
tRCH
tRRH
tWCS
tWCH
tWP
tWCR
Min
90
120
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
7
9
10
11
4
Notes
4,5,10,11
4,5,10
4,5,11
3
0
0
2
30
50
15
45
8
15
10
5
7
0
8
0
8
45
25
0
0
0
0
10
10
40
Output buffer turn-off delay from
CAS
Transition time (rise and fall)
RAS
precharge time
RAS
pulse width
RAS
hold time
CAS
hold time
CAS
pulse width
RAS
to
CAS
delay time
RAS
to column address delay time
CAS
to
RAS
precharge time
CAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address hold time ref. to
RAS
Column address to
RAS
lead time
Read command set-up time
Read command hold time ref. to
CAS
Read command hold time ref. to
RAS
Write command set-up time
Write command hold time
Write command pulse width
Write command hold time from RAS
Revision: A
Revision Date: 1/2000
Document number: 44605
page number: 4 of 7
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVED16F664LSD8TS-XX
16M X 64 DRAM SODIMM, EDO MODE, Using 8M X 8 Stacked, 4K Refresh, 3.3V
AC CHARACTERISITICS
(continued)
-50
STAND
ANDARD
STANDARD
OPERATION
OPERATION
Symbol
tRWL
tCWL
tDS
tDH
tREF
tCWD
tRWD
tAWD
tCSR
tCHR
tRPC
tCPA
tHPC
20
50
25
0
50
10
10
13
13
13
5
5
5
0
5
0
0
15
5
100
100
-50
45
30
10
10
10
10
10
15
15
5
5
5
0
5
0
0
15
5
100
100
-50
54
35
10
10
15
15
15
100K
34
70
45
5
10
5
30
25
60
30
0
60
10
10
15
100K
-60
Max
Min
15
10
0
10
64
36
80
50
5
10
5
35
64
Min
15
8
0
10
Max
Unit
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
Notes
Write command to
RAS
lead time
Write command to
CAS
lead time
Data set-up time
Data hold time
Refresh period (4K)
CAS to W delay time
RAS to W delay time
Column address to
W
delay time
CAS
set-up time
(
CAS
- before -
RAS
refresh)
CAS
hold time (
CAS
- before -
RAS
refresh)
RAS
to
CAS
precharge time
8
8
12
9
9
9
Access time from
CAS
precharge
Hyper Page mode cycle time
Hyper Page mode read-modify-write
cycle
CAS Precharge Time (C-B-R counter test)
RAS Hold Time referenced to OE
RAS
pulse width (EDO mode)
W
to
RAS
precharge time
(
C
-B-
R
refresh)
W
to
RAS
hold time
(
C
-B-
R
refresh)
4
t
HPRWC
tCPT
tROH
tRASP
tWRP
tWRH
tOEA
tOED
tOEH
tOCH
tCHO
tOEP
tOEZ
tDOH
tREZ
tWEZ
tWED
tWPE
tRASS
tRPS
tCHS
tCPWD
tRHCP
tWTS
tWTH
OE access time
OE to data delay
OE command hold time
OE to CAS hold time
CAS hold time to OE
OE precharge time
Output buffer turn off delay time from OE
Output data hold time
Output buffer turn off delay from
RAS
Output buffer turn off delay from
W
W
to data delay
W
pulse width (EDO cycle)
6
6
6
RAS pulse width (C-B-R self-refresh)
RAS precharge time (C-B-R self-refresh)
CAS hold time (C-B-R self-refresh)
W delay time from CAS precharge
RAS hold time from CAS precharge
Write command set-up time (test mode)
Write command hold time (test mode)
Revision: A
Revision Date: 1/2000
Document number: 44605
page number: 5 of 7
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