5P49V6975A000LTGI datasheet, PDF

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5P49V6975A000LTGI: DescriptionVERSACLOCK 6E W/ INTEGRATED CRYS; Categorysemiconductor Analog mixed-signal IC; File Size895KB，28 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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5P49V6975A000LTGI Overview

VERSACLOCK 6E W/ INTEGRATED CRYS

5P49V6975A000LTGI Parametric

Parameter Name	Attribute value
type	clock generator
PLL	With bypass
enter	HCSL, LVCMOS, LVDS, LVPECL, crystal
output	HCSL，LVCMOS，LVDS，LVPECL
Number of circuits	1
Ratio - Input:Output	2：4
Differential - Input:Output	Yes Yes
Frequency - maximum	350MHz
Frequency divider/multiplier	yes/no
Voltage - Power	1.71 V ~ 3.465 V
Operating temperature	-40°C ~ 85°C
Installation type	surface mount
Package/casing	24-LFLGA Exposed Pad
Supplier device packaging	24-LGA（4x4）

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VersaClock

6E Programmable

Clock with Internal Crystal

Description

The 5P49V6975 is a programmable clock generator intended for

high-performance consumer, networking, industrial, computing,

and data-communications applications. The device is a member of

IDT’s sixth generation of programmable clock technology,

VersaClock 6E.

The 5P49V6975 contains an internal crystal, which eliminates the

need for external crystal and load cap tuning.

Two select pins allow up to four different configurations to be

programmed, and can be used for different operating modes (full

function, partial function, partial power-down), regional standards

(US, Japan, Europe) or system production margin testing. The

5P49V6975 can be configured to use one of two I

C addresses to

allow the use of multiple devices in a system.

5P49V6975

Datasheet

Features



Typical Applications



Ethernet switch/router

PCI Express 1–4

Broadcast video/audio timing

Multi-function printer

Processor and FPGA clocking

Any-frequency clock conversion

MSAN/DSLAM/PON

Fiber Channel, SAN

Telecom line cards

Laser distance sensing



Internal crystal input integrated into package

Flexible 1.8V, 2.5V, 3.3V power rails

High-performance, low phase noise PLL, < 0.5ps RMS typical

phase jitter on outputs

Four banks of internal OTP memory

— In-system or factory programmable

— Two select pins accessible with processor GPIOs or

bootstrapping

C serial programming interface

— 0xD0 or 0xD4 I

C address options allow multiple devices

configured in a same system

Reference LVCMOS output clock

Four universal output pairs individually configurable:

— Differential (LVPECL, LVDS, or HCSL)

— Two single-ended (2 LVCMOS in-phase or 180 degrees

out of phase)

— I/O VDDs can be mixed and matched, supporting 1.8V

(LVDS and LVCMOS), 2.5V, or 3.3V

— Independent spread spectrum on each output pair

Output frequency ranges:

— LVCMOS clock outputs: 1kHz to 200MHz

— LVDS, LVPECL, HCSL differential clock outputs: 1kHz to

350MHz

Programmable output enable or power-down mode

Available in 4 × 4 mm 24-LGA package

-40° to +85°C industrial temperature operation

Block Diagram

DDO

OUT0_SEL_I2CB

DDO

CLKIN

CLKINB

CLKSEL

SD/OE

SEL1/SDA

SEL0/SCL

DDA

DDD

OTP

and

Control

Logic

FOD2

PLL

OUT1

FOD1

OUT1B

DDO

OUT2

OUT2B

DDO

FOD3

OUT3

OUT3B

DDO

FOD4

OUT4

OUT4B

April 27, 2018

5P49V6975 Datasheet

Contents

Pin Assignments ...........................................................................................................................................................................................3

Pin Descriptions............................................................................................................................................................................................3

Absolute Maximum Ratings ..........................................................................................................................................................................5

Thermal Characteristics................................................................................................................................................................................5

Recommended Operating Conditions ..........................................................................................................................................................5

Electrical Characteristics ..............................................................................................................................................................................6

Test Loads ..................................................................................................................................................................................................13

Jitter Performance Characteristics .............................................................................................................................................................14

PCI Express Jitter Performance and Specification .....................................................................................................................................15

10.1 Device Startup and Power-on-Reset................................................................................................................................................16

10.2 Reference Clock and Selection ........................................................................................................................................................17

10.3 Manual Switchover ...........................................................................................................................................................................17

10.4 Programmable Loop Filter................................................................................................................................................................18

10.5 Fractional Output Dividers (FOD).....................................................................................................................................................18

10.5.1

10.5.2

10.5.3

10.5.4

10.5.5

Individual Spread Spectrum Modulation ...........................................................................................................................18

Bypass Mode ....................................................................................................................................................................18

Cascaded Mode ................................................................................................................................................................18

Dividers Alignment ............................................................................................................................................................18

Programmable Skew .........................................................................................................................................................19

10. Features and Functional Blocks .................................................................................................................................................................16

10.6 Output Drivers ..................................................................................................................................................................................19

10.7 SD/OE Pin Function .........................................................................................................................................................................19

10.8 I

C Operation ...................................................................................................................................................................................20

11. Typical Application Circuit ..........................................................................................................................................................................21

11.1 Input – Driving the CLKIN ................................................................................................................................................................22

11.1.1

11.1.2

11.2.1

11.2.2

11.2.3

11.2.4

Wiring the CLKIN Pin to Accept Single-Ended Inputs .......................................................................................................22

Driving CLKIN with Differential Clock ................................................................................................................................23

LVDS Termination .............................................................................................................................................................23

LVPECL Termination ........................................................................................................................................................24

HCSL Termination.............................................................................................................................................................25

LVCMOS Termination .......................................................................................................................................................25

11.2 Output – Single-ended or Differential Clock Terminations ...............................................................................................................23

12. Package Outline Drawings .........................................................................................................................................................................25

13. Marking Diagram .........................................................................................................................................................................................26

14. Ordering Information ...................................................................................................................................................................................26

15. Revision History ..........................................................................................................................................................................................26

April 27, 2018

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