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DA7212-01UM2

Description
IC AUDIO CODEC 34CSP
Categorysemiconductor    Analog mixed-signal IC   
File Size2MB,3 Pages
ManufacturerMaxLinear
Environmental Compliance
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DA7212-01UM2 Overview

IC AUDIO CODEC 34CSP

DA7212-01UM2 Parametric

Parameter NameAttribute value
typeAudio
Data interface-
Resolution (bits)-
ADC/DAC number2 / 2
Trigonometric integralyes
Signal-to-noise ratio, ADC/DAC (db) (typ)90 / 100
Dynamic range, ADC/DAC (db) (typ)-
Voltage - Power, Analog1.7 V ~ 2.5 V
Voltage - Power, Digital1.6 V ~ 3.6 V
Operating temperature-40°C ~ 85°C
Installation typesurface mount
Package/casing34-UFBGA,CSPBGA
Supplier device packaging34-CSP(4.5x1.66)
DA7212
Stereo CODEC with enhanced automatic level controller
and 1.2W speaker driver
DA7212 is a high performance, low-power audio codec with
an enhanced hybrid ALC and a powerful speaker driver
targeting portable and embedded applications.
A key benefit of the DA7212 is that it operates from a single
supply and has an internal LDO that can be used to optimise
power consumption.
The audio front-end simultaneously supports stereo auxiliary
line inputs plus analogue and digital microphones with two
independent microphone biases. These inputs can be mixed into
the input and/or output mixer paths.
34 ball WL_CSP Package, 0.5mm pitch
The audio/voice capture path also integrates an enhanced ALC and noise gate function to ensure
the dynamic range of the stereo ADCs is maximised. Comprehensive analogue mixing and bypass
paths to the output drivers are available.
The playback path delivers 98dB into 16Ω stereo headphones whilst only consuming 6.9mW (under
JEITA conditions). The headphone driver is true-ground with built-in charge pump. A dedicated
mono speaker channel is available that can deliver 1.2W into 8Ω mini-speaker when supplied from
5.0V.
All High pass channel filtering is performed digitally. Other digital functions include programmable
5-band EQ, beep generator and wind noise filter.
The codec supports both master and slave mode operation using the internal PLL which may
be bypassed if not required. The low power fractional PLL has been optimised to support a wide
range of sample and reference clock frequencies. Internal suppression circuits help maintain audio
synchronisation in the presence of system noise on the external clock.
Digital audio transfer to and from the external processor is available via bidirectional I2S interface
which supports all common sample rates.
www.dialog-semiconductor.com

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