Product Specifications
PART NO.:
VL47D5763A-K0SD-S1
REV: 1.0
General Information
2GB 256Mx64 DDR3 SDRAM LOW VOLTAGE NON-ECC UNBUFFERED SODIMM 204-PIN
Description
The VL47D5763A is a 256Mx64 DDR3 SDRAM high density SODIMM. This single rank memory module consists of
eight CMOS 256Mx8 bits with 8 banks DDR3 Synchronous DRAMs in BGA packages and a 2K EEPROM with
thermal sensor in an 8-pin MLF package. This module is a 204-pin small-outline dual in-line memory module and is
intended for mounting into an edge connector socket. Decoupling capacitors are mounted on the printed circuit board
for each DDR3 SDRAM.
Features
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204-pin, small-outline dual in-line memory module (SODIMM)
Fast data transfer rate: PC3-12800
VDD = VDDQ = 1.35V (1.28V~1.45V) & 1.5V (1.425V~1.575V)
JEDEC standard 1.35V (1.28V~1.45V) & 1.5V (1.425V~1.575V)
VDDSPD = 3.0V to 3.6V
Eight internal component banks for concurrent operation
8-bit pre-fetch architecture
Bi-directional differential data-strobe
Nominal and dynamic on-die termination (ODT)
ZQ calibration support
Programmable CAS# latency: 11 (DDR3-1600)
Programmable burst; length (8)
Average refresh period 7.8 us
Asynchronous reset
Fly-by topology
On board terminated command, address, and control bus
Serial presence detect (SPD) EEPROM with thermal sensor
o
o
o
Thermal sensor range: -40 C to +125 C (Max +/-3 C accuracy)
Lead-free, RoHS compliant
Gold edge contacts
PCB: Height 30.00mm (1.181”), double sided component
o
o
Operating temperature (T
OPER
): -40 C to +95 C (module screening using
commercial DRAM)
Notes: Double refresh rate is required when 85 C < T
OPER
<= 95 C.
T
OPER
is DRAM case temperature (Tc).
o
o
Pin Description
Pin Name
A0~A14
A10/AP
A12/BC#
BA0~BA2
DQ0~DQ63
DQS0~DQS7
DQS0#~DQS7#
DM0~DM7
CK0,CK0#
ODT0
CKE0
CS0#
RAS#
CAS#
WE#
VDD
VSS
SA0~SA1
SDA
SCL
EVENT#
Function
Address Inputs
Address Input/ Autoprecharge
Address Input/ Burst Chop
Bank Address Inputs
Data Input/Output
Data Strobes
Data Strobes Complement
Data Masks
Clock Input
On-die Termination Control
Clock Enables
Chip Selects
Row Address Strobes
Column Address Strobes
Write Enable
Voltage Supply
Ground
SPD Address
SPD Data Input/Output
SPD Clock Input
Temperature Event Output
Reference Voltage for CA
Reference Voltage for DQ
SPD Voltage Supply
Termination Voltage
Register and SDRAM Control
No Connect
Order Information:
VL47D5763A - K0 S D - S1
OPERATING TEMPERATURE
S1:
Industrial screening
VREFCA
VREFDQ
VDDSPD
VTT
RESET#
NC
DRAM DIE
D-DIE
DRAM MANUFACTURER
S - SAMSUNG
MODULE SPEED
K0: PC3-12800 @ CL11
VL: Lead-free/RoHS
DRAM component: Samsung K4B2G0846D-HYK0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA –
www.virtium.com
1
Product Specifications
PART NO.:
VL47D5763A-K0SD-S1
REV: 1.0
Pin Configuration
204-PIN DDR3 SODIMM FRONT
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Name
VREFDQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
Pin
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
Name
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
Pin
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
Name
VDD
A10
BA0
VDD
WE#
CAS#
VDD
A13
CS1# *
VDD
NC
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
Pin
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
Name
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
Name
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
204-PIN DDR3 SODIMM BACK
Pin
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
Name
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1*
VDD
A15 *
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1*
CK1#*
Pin
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
Name
VDD
BA1
RAS#
VDD
CS0#
ODT0
VDD
ODT1*
NC
VDD
VREFCA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
Pin
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
Name
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
*: These pins are not used in this module.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA –
www.virtium.com
2
Product Specifications
PART NO.:
VL47D5763A-K0SD-S1
REV: 1.0
Function Block Diagram
CS0#
DQS0
DQS0#
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS1#
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS3#
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
ZQ
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
ZQ
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
ZQ
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
ZQ
DQS4
DQS4#
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Vss
DQS5
DQS5#
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Vss
DQS6
DQS6#
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Vss
DQS7
DQS7#
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Vss
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
ZQ
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
ZQ
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
ZQ
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
ZQ
D0
D4
Vss
D1
D5
Vss
D2
D6
Vss
D3
D7
Vss
A0-A14
BA0-BA2
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
A0-A14: SDRAMs D0-D7
BA0-BA2: SDRAMs D0-D7
RAS#: SDRAMs D0-D7
CAS#: SDRAMs D0-D7
WE#: SDRAMs D0-D7
CKE0: SDRAMs D0-D7
ODT0: SDRAMs D0-D7
RESET#: SDRAMs D0-D7
Command, address, control, and clock line terminations
A0-A14, BA0-BA2
RAS#, CAS#, WE#,
CS0#, CKE0, ODT0
DDR3
SDRAM
39 ohm +/-5%
VTT
36 ohm +/-5%
CK0
CK0#
DDR3
SDRAM
VDD
0.1uF
CK0
D0-D7
CK0#
Serial PD
w ith integrated thermal sensor
SCL
SDA
EVENT#
A0
A1
A2
3.3pF
VDDSPD
VDD
VTT
Serial PD/
Thermal sensor
D0-D7
D0-D7
D0-D7
D0-D7
D0-D7
EVENT#
SA0 SA1 Vss
Notes:
1. Unless otherw ise noted, resistor values are 15 ohms +/-5%
2. ZQ resistors are 240 ohms +/-1%
VREFCA
VREFDQ
VSS
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA –
www.virtium.com
3
Product Specifications
PART NO.:
VL47D5763A-K0SD-S1
REV: 1.0
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VIN, VOUT
TSTG
Parameter
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on any pin relative to VSS
Storage temperature
Address, RAS#,
CAS#, WE#, BA
CS#, CKE, ODT,
CK, CK#
DM
Min
-0.4
-0.4
-0.4
-55
-16
-16
-2
-5
-8
Max
1.975
1.975
1.975
100
16
16
2
5
8
Unit
V
V
V
0
C
uA
uA
uA
uA
uA
IL
Input leakage current; Any input 0V<VIN<VDD;
VREF input 0V<VIN<0.95V;
Other pins not under test = 0V
IOZ
IVREF
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT are disabled
DQ, DQS, DQS#
VREF supply leakage current; VREF = Valid VREF level
DC Operating Conditions
Symbol
VDD
Parameter
Supply Voltage
Operating Voltage
1.35V
1.5V
1.35V
Min
1.283
1.425
1.283
1.425
0.49 x VDD
0.49 x VDD
-0.483 x VDDQ
Typical
1.35
1.5
1.35
1.5
0.5 x VDD
0.5 x VDD
0.5 x VDDQ
Max
1.45
1.575
1.45
Unit Notes
V
1,2
VDDQ
VREFDQ (DC)
VREFCA (DC)
VTT
I/O Supply Voltage
1.5V
I/O reference voltage DQ bus
Input reference voltage CMD/ADD bus
Termination Reference Voltage
1.575
0.51 x VDD
0.51 x VDD
+0.517 x VDDQ
V
V
V
V
1,2
3,4
3,4
5
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/-1% VDD
4. For reference: approximate VDD/2 +/-15mV.
5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals’ voltage margin and will reduce
timing margins.
Operating Temperature Condition
Symbol
T
OPER
Parameter
Operating temperature
Rating
-40 to +95
Units
0
Notes
1,2
C
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JEDEC JESD51-2.
o
2. At -40 to +85 C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
o
o
85 C < TOPER <= 95 C.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA –
www.virtium.com
4
Product Specifications
PART NO.:
VL47D5763A-K0SD-S1
REV: 1.0
Input DC Logic Level
All voltages referenced to VSS
Symbol
Command and Address
VIHCA(DC)
VILCA(DC)
DQ and DM
VIHDQ(DC)
VILDQ(DC)
Input High (Logic 1)
Input Low (Logic 0)
Input High (Logic 1)
Input Low (Logic 0)
Parameter
1.35V
Min
Max
Unit
VREF + 0.090
VSS
VDD
VREF - 0.090
V
V
VREF + 0.090
VSS
1.5V
VDD
VREF - 0.090
V
V
Command and Address
VIHCA(DC)
VILCA(DC)
DQ and DM
VIHDQ(DC)
VILDQ(DC)
Input High (Logic 1)
Input Low (Logic 0)
VREF + 0.100
VSS
VDD
VREF – 0.100
V
V
Input High (Logic 1)
Input Low (Logic 0)
VREF + 0.100
VSS
VDD
VREF - 0.100
V
V
Input AC Logic Level
All voltages referenced to VSS
Symbol
Parameter
1.35V
Min
Max
Unit
Command and Address
VIHCA(AC)
VILCA(AC)
DQ and DM
VIHDQ(AC)
VILDQ(AC)
Input High (Logic 1)
Input Low (Logic 0)
1.5V
Command and Address
VIHCA(AC)
VILCA(AC)
DQ and DM
VIHDQ(AC)
VILDQ(AC)
Input High (Logic 1)
Input Low (Logic 0)
VREF + 0.150
-
-
VREF - 0.150
V
V
Input High (Logic 1)
Input Low (Logic 0)
VREF + 0.175
-
-
VREF - 0.175
V
V
VREF + 0.135
-
-
VREF - 0.135
V
V
Input High (Logic 1)
Input Low (Logic 0)
VREF + 0.160
-
-
VREF - 0.160
V
V
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA –
www.virtium.com
5
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