®
X5328, X5329
(Replaces X25328, X25329)
Data Sheet
October 17, 2005
FN8132.1
CPU Supervisor with 32Kbit SPI EEPROM
FEATURES
• Low V
CC
detection and reset assertion
—Five standard reset threshold voltages
—Re-program low V
CC
reset threshold voltage
using special programming sequence
—Reset signal valid to V
CC
= 1V
• Long battery life with low power consumption
—<1µA max standby current
—<400µA max active current during read
• 32Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock
™
protection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
WP
SI
SO
SCK
CS
Data
Register
Command
Decode &
Control
Logic
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Supply Voltage Supervision, and Block
Lock Protect Serial EEPROM Memory in one package.
This combination lowers system cost, reduces board
space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions by holding
RESET/RESET active when V
CC
falls below a mini-
mum V
CC
trip point. RESET/RESET remains asserted
until V
CC
returns to proper operating level and stabi-
lizes. Five industry standard V
TRIP
thresholds are
available, however, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold in applica-
tions requiring higher precision.
Protect Logic
Status
Register
EEPROM Array
8Kbits
8Kbits
16Kbits
Reset
Timebase
RESET/RESET
V
CC
V
TRIP
+
-
Power-on and
Low Voltage
Reset
Generation
X5328 = RESET
X5329 = RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5328, X5329
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
X5328P-4.5A
X5328PZ-4.5A (Note)
X5328PI-4.5A
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
X5329P-4.5A
X5328P Z AL X5329PZ-4.5A (Note)
X5329PI-4.5A
X5329P Z AL
PART
MARKING
V
CC
RANGE
TEMP
(V)
V
TRIP
RANGE RANGE (°C)
4.5-5.5
4.5-4.75
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
X5329 Z AM
-40 to 85
0 to 70
X5329V Z AL
0 to 70
-40 to 85
X5329V Z AM
X5329P
X5329P Z
X5329P I
X5329P Z I
4.5-5.5
4.25-4.5
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
X5329 Z
0 to 70
-40 to 85
X5329 Z I
-40 to 85
0 to 70
X5329V Z
0 to 70
-40 to 85
X5329V Z I
2.7-5.5
X5329P Z AN
2.85-3.0
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
X5329 Z AP
-40 to 85
0 to 70
X5329V Z AN
0 to 70
PACKAGE
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
X5328PIZ-4.5A (Note) X5328P Z AM X5329PIZ-4.5A (Note) X5329P Z AM
X5328S8-4.5A
X5328 AL
X5329S8-4.5A
X5329S8Z-4.5A (Note) X5329 Z AL
X5329S8I-4.5A
X5329S8IZ-4.5A
(Note)
X5329V14-4.5A
X5328V Z AL X5329V14Z-4.5A
(Note)
X5329V14I-4.5A
X5328V Z AM X5329V14IZ-4.5A
(Note)
X5328P
X5328P Z
X5328P I
X5328P Z I
X5328
X5328 Z
X5328 I
X5328 Z I
X5328V
X5328V Z
X5329P
X5329PZ (Note)
X5329PI
X5329PIZ (Note)
X5329S8*
X5329S8Z* (Note)
X5329S8I*
X5329S8IZ* (Note)
X5329V14*
X5329V14Z* (Note)
X5329V14I*
X5328V Z I
X5329V14IZ* (Note)
X5329P-2.7A
X5328P Z AN X5329PZ-2.7A (Note)
X5329PI-2.7A
X5328S8Z-4.5A (Note) X5328 Z AL
X5328S8I-4.5A
X5328S8IZ-4.5A
(Note)
X5328V14-4.5A
X5328V14Z-4.5A
(Note)
X5328V14I-4.5A
X5328V14IZ-4.5A
(Note)
X5328P
X5328PZ (Note)
X5328PI
X5328PIZ (Note)
X5328S8*
X5328S8Z* (Note)
X5328S8I*
X5328S8IZ* (Note)
X5328V14*
X5328V14Z* (Note)
X5328V14I*
X5328V14IZ* (Note)
X5328P-2.7A
X5328PZ-2.7A (Note)
X5328PI-2.7A
X5328 AM
X5328 Z AM
X5328PIZ-2.7A (Note) X5328P Z AP X5329PIZ-2.7A (Note) X5329P Z AP
X5328S8-2.7A
X5328 AN
X5329S8-2.7A
X5329S8Z-2.7A (Note) X5329 Z AN
X5329S8I-2.7A
X5329S8IZ-2.7A
(Note)
X5329V14-2.7A
X5328S8Z-2.7A (Note) X5328 Z AN
X5328S8I-2.7A
X5328S8IZ-2.7A
(Note)
X5328V14-2.7A
X5328V14Z-2.7A
(Note)
X5328 AP
X5328 Z AP
X5328V AN
X5328V Z AN X5329V14Z-2.7A
(Note)
2
FN8132.1
October 17, 2005
X5328, X5329
Ordering Information
(Continued)
PART NUMBER
RESET
(ACTIVE LOW)
X5328V14I-2.7A
X5328V14IZ-2.7A
(Note)
X5328P-2.7
X5328PZ-2.7 (Note)
X5328PI-2.7
X5328PIZ-2.7 (Note)
X5328S8-2.7*
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
X5329V14I-2.7A
X5328V Z AP X5329V14IZ-2.7A
(Note)
X5328P F
X5328P Z F
X5328P G
X5328P Z G
X5328 F
X5329P-2.7
X5329PZ-2.7 (Note)
X5329PI-2.7
X5329PIZ-2.7 (Note)
X5329S8-2.7*
X5329S8Z-2.7* (Note) X5329 Z F
X5329S8I-2.7*
X5329S8IZ-2.7* (Note) X5329 Z G
X5329V14-2.7*
X5328V Z F
X5329V14Z-2.7*
(Note)
X5329V14I-2.7*
X5328V Z G
X5329V14IZ-2.7*
(Note)
X5329V Z G
X5329V Z F
X5329V Z AP
X5329P F
X5329P Z F
X5329P G
X5329P Z G
2.7-5.5
2.55-2.7
PART
MARKING
V
CC
RANGE
TEMP
(V)
V
TRIP
RANGE RANGE (°C)
2.7-5.5
2.85-3.0
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
X5328S8Z-2.7* (Note) X5328 Z F
X5328S8I-2.7*
X5328 G
X5328S8IZ-2.7* (Note) X5328 Z G
X5328V14-2.7*
X5328V14Z-2.7*
(Note)
X5328V14I-2.7*
X5328V14IZ-2.7*
(Note)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3
FN8132.1
October 17, 2005
X5328, X5329
PIN DESCRIPTION
Pin
(SOIC/PDIP)
1
Pin
TSSOP
1
Name
CS
Function
Chip Select Input.
CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and out-
put. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the Watchdog Timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output.
RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever V
CC
falls below the minimum V
CC
sense level. It
will remain active until V
CC
rises above the minimum V
CC
sense level for 200ms.
RESET/RESET goes active on power-up at about 1V and remains active for
200ms after the power supply stabilizes.
No internal connections
2
5
2
8
SO
SI
6
9
SCK
3
4
8
7
6
7
14
13
WP
V
SS
V
CC
RESET/
RESET
3-5,10-12
NC
PIN CONFIGURATION
14 Ld TSSOP
8 Ld SOIC/PDIP
CS
SO
WP
V
CC
1
2
3
4
X5328/29
8
7
6
5
V
CC
RESET/RESET
SCK
SI
CS
SO
NC
NC
NC
WP
V
SS
1
2
3
14
13
12
V
CC
RESET/RESET
NC
NC
NC
SCK
SI
4
X5328/29
11
5
6
7
10
9
8
4
FN8132.1
October 17, 2005
X5328, X5329
PRINCIPLES OF OPERATION
Power-On Reset
Application of power to the X5328/X5329 activates a
Power-on Reset Circuit. This circuit goes active at
about 1V and pulls the RESET/RESET pin active. This
signal prevents the system microprocessor from start-
ing to operate with insufficient voltage or prior to stabi-
lization of the oscillator. When V
CC
exceeds the device
V
TRIP
value for 200ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin exe-
cuting code.
Low Voltage Monitoring
During operation, the X5328/X5329 monitors the V
CC
level and asserts RESET/RESET if supply voltage
falls below a preset minimum V
TRIP
. The
RESET/RESET signal prevents the microprocessor
from operating in a power fail or brownout condition.
The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until
V
CC
returns and exceeds V
TRIP
for 200ms.
V
CC
Threshold Reset Procedure
The X5328/X5329 has a standard V
CC
threshold
(V
TRIP
) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard V
TRIP
is not exactly right, or
for higher precision in the V
TRIP
value, the
X5328/X5329 threshold may be adjusted.
Setting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a higher voltage
value. For example, if the current V
TRIP
is 4.4V and
the new V
TRIP
is 4.6V, this procedure directly makes
the change. If the new setting is lower than the current
setting, then it is necessary to reset the trip point
before setting the new value.
To set the new V
TRIP
voltage, apply the desired V
TRIP
threshold to the V
CC
pin and tie the CS pin and the WP
pin HIGH. RESET/RESET and SO pins are left uncon-
nected. Then apply the programming voltage V
P
to
both SCK and SI and pulse CS LOW then HIGH.
Remove V
P
and the sequence is complete.
SCK
V
CC
CS
V
P
SCK
V
P
SI
Figure 1. Set V
TRIP
Voltage
Resetting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a “native” voltage
level. For example, if the current V
TRIP
is 4.4V and the
V
TRIP
is reset, the new V
TRIP
is something less than
1.7V. This procedure must be used to set the voltage
to a lower value.
To reset the V
TRIP
voltage, apply a voltage between
2.7 and 5.5V to the V
CC
pin. Tie the CS pin, the WP
pin, and the SCK pin HIGH. RESET/RESET and SO
pins are left unconnected. Then apply the program-
ming voltage V
P
to the SI pin ONLY and pulse CS
LOW then HIGH. Remove V
P
and the sequence is
complete.
Figure 2. Reset V
TRIP
Voltage
CS
V
P
SI
5
FN8132.1
October 17, 2005
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