SL28506
Clock Generator for Intel
®
Eaglelake Chipset
Features
• Intel
®
CK505 Rev. 1.0 Compliant
• Low power push-pull type differential output buffers
• PCI-Express Gen 2 Compliant SRC clocks (exclude
SRC0 and SRC1)
• 8-step programmable drive strength for single-ended
clocks
• Differential CPU clocks with selectable frequency
• 100 MHz Differential SRC clocks
• 100 MHz Differential LCD clock
• 96 MHz Differential DOT clock
• 48 MHz USB clock
• 33 MHz PCI clocks
• 27MHz non-spread Video clock
• 25 MHz Video clocks
• 1396 Firewire clock
• Buffered Reference Clock 14.318 MHz
• 14.318 MHz Crystal Input or Clock Input
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Industrial Temperature -40°C to 85°C
• 3.3V Power supply
•
64-pinTSSOP packages
CPU
SRC
PCI REF DOT96 USB_48 LCD
x6
x1
x1
x1
x1
SE
x2
x2 / x3 x7/12
Block Diagram
PCI0/OE#_0/2_A
VDD_PCI
PCI1/OE#_0/2_A
PCI2/TME
PCI3/CFG0*
PCI4/ SRC5_EN
PCIF0/ITP_EN
VSS_PCI
VDD_48
USB_48/ FSA
VSS_48
VDD_IO
SRC0/DOT96
SRC0#/DOT96#
VSS_IO
VDD_PLL3
SRC1/LCD100/SE1
SRC1#/LCD100#/SE2
VSS_PLL3
VDD_PLL3_IO
SRC2/SATA
SRC2#/SATA#
VSS_SRC
SRC3/OE#_0/2_B
SRC3#/OE#_1/4_B
VDD_SRC_IO
SRC4
SRC4#
VSS_SRC
SRC9
SRC9#
SRC11#//OE#_9
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK
SDATA
REF0/FSC/TEST_SEL
VDD_REF
XIN/CLKIN
XOUT
VSS_REF
FSB/TEST_MODE
CKPWRGD/PD#
VDD_CPU
CPU0
CPU#0
VSS_CPU
CPU1
CPU1#
VDD_CPU_IO
IO_VOUT
SRC8/ CPU2_ITP
SRC8#/ CPU2_ITP#
VDD_SRC_IO
SRC7/OE#_8
SRC7#/OE#_6
VSS_SRC
SRC6
SRC#
VDD_SRC
SRC5/PCI_STP#
SRC5#/CPU_STP#
VDD_SRC_IO
SRC10#
SRC10
SRC11/OE#_10
* 100K-ohm Internal Pull Down
......................... DOC #: SP-AP-0021 (Rev AA) Page 1 of 28
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL28506
64 TSSOP Pin Definition
Pin No.
Name
1
PCI0/OE#_0/2_A
2
3
4
5
VDD_PCI
PCI1/OE#_1/4_A
PCI2/TME
PCI3/CFG0
Type
Description
I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC0 or
SRC2.
(Default PCI0, 33MHz clock)
PWR
3.3V Power supply for PCI PLL.
I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC1 or
SRC4.
(Default PCI1, 33MHz clock)
I/O, SE 3.3V tolerance input for overclocking enable pin/3.3V, 33MHz clock.
(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)
I/O, SE, 3.3V tolerant input for CPU frequency selection/3.3V 33MHz clock.
PD
(Refer to DC Electrical Specifications table for Vil_PCI3/CFG0 and
Vih_PCI3/CFG0 specifications).
6
PCI4/SRC5_EN
I/O, SE 3.3V tolerant input to enable SRC5/3.3V, 33MHz clock.
(Sampled on the CKPWRGD assertion)
1 = SRC5, 0 = CPU_STP#
I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/3.3V, 33MHz clock.
(Sampled on the CKPWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
GND
PWR
I/O
GND
PWR
Ground for outputs.
3.3V Power supply for outputs and PLL.
3.3V tolerant input for CPU frequency selection/fixed 3.3V, 48MHz clock output.
(Refer
to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)
Ground for outputs.
0.7V Power supply for outputs.
7
PCIF/ITP_EN
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS_PCI
VDD_48
USB_48/FSA
VSS_48
VDD_IO
SRC0/DOT96
SRC0#/DOT96#
VSS_IO
VDD_PLL3
SRC1/LCD100/SE1
SRC1#/LCD100#/SE2
VSS_PLL3
VDD_PLL3_IO
SRC2/SATA
SRC2#/SATA#
VSS_SRC
SRC3/OE#_0/2_B
SRC3#OE#_1/4_B
O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.
(Selected via I2C default is SRC0)
O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.
(Selected via I2C default is SRC0)
GND
PWR
Ground for PLL2.
3.3V Power supply for PLL3
O, DIF, 100MHz Differential serial reference clocks/100MHz LCD video clock/SE1 clocks.
SE
(Default SRC1, 100MHz clock)
O, DIF, 100MHz Differential serial reference clocks/100MHz LCD video clock/SE2 clocks.
SE
(Default SRC1, 100MHz clock)
GND
PWR
Ground for PLL3.
IO Power supply for PLL3 outputs.
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
GND
I/O,
Dif
I/O,
Dif
Ground for outputs.
100MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable
via I2C to control either SRC0 or SRC2.
(Default SRC3, 100MHz clock)
100MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable
via I2C to control either SRC1 or SRC4.
(Default SRC3, 100MHz clock)
.........................DOC #: SP-AP-0021 (Rev AA) Page 2 of 28
SL28506
64 TSSOP Pin Definition
(continued)
Pin No.
Name
26
VDD_SRC_IO
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
SRC4
SRC4#
VSS_SRC
SRC9
SRC9#
SRC11#/OE#_9
SRC11/OE#_10
SRC10
SRC10#
VDD_SRC_IO
SRC5#CPU_STP#
SRC5/PCI_STP#
VDD_SRC
SRC6#
SRC6
VSS_SRC
SRC7#/OE#_6
SRC7/OE#_8
VDD_SRC_IO
SRC8#/CPU2#_ITP#
Type
PWR
Description
IO power supply for SRC outputs.
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
GND
Ground for outputs.
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
I/O,
Dif
I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9
(Default SRC11, 100MHz clock)
100MHz Differential serial reference clocks/3.3V OE#10 Input controlling SRC10.
(Default SRC11, 100MHz clock)
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
PWR
I/O,
Dif
I/O,
Dif
PWR
IO Power supply for SRC outputs.
3.3V tolerant input for stopping CPU outputs/100MHz Differential serial reference
clocks.
3.3V tolerant input for stopping PCI and SRC outputs/100MHz Differential serial
reference clocks.
3.3V Power supply for SRC PLL.
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
GND
I/O,
Dif
I/O,
Dif
PWR
Ground for outputs.
100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6.
(Default SRC7, 100MHz clock).
100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
(Default SRC7, 100MHz clock).
0.7V power supply for SRC outputs.
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
47
SRC8/CPU2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
48
49
50
51
52
53
54
55
56
IO_VOUT
VDD_CPU_IO
CPU1#
CPU1
VSS_CPU
CPU#0
CPU0
VDD_CPU
CKPWRGD/PD#
PWR
PWR
Integrated Linear Regulator Control.
IO Power supply for CPU outputs.
on the configuration set in Byte 11 Bit3:2)
O, DIF Differential CPU clock outputs. (
Note: CPU1 is an iAMT clock in iAMT mode depending
O, DIF Differential CPU clock outputs. (
Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
GND
Ground for outputs.
O, DIF Differential CPU clock outputs.
O, DIF Differential CPU clock outputs.
PWR
I
3.3V Power supply for CPU PLL.
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
.........................DOC #: SP-AP-0021 (Rev AA) Page 3 of 28
SL28506
64 TSSOP Pin Definition
(continued)
Pin No.
Name
57
FSB/TEST_MODE
Type
I
Description
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal.
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output.
Selects test mode if pulled to V
IHFS_C
when CKPWRGD is asserted HIGH.
Refer
to DC Electrical Specifications table for
V
ILFS_C
, V
IMFS_C
, V
IHFS_C
specifications.
SMBus compatible SDATA.
SMBus compatible SCLOCK.
58
59
60
61
62
VSS_REF
XOUT
XIN/CLKIN
VDD_REF
REF0/FSC/TEST_SEL
GND
I
PWR
I/O
O, SE 14.318MHz Crystal output.
(Float XOUT if using CLKIN)
63
64
SMB_DATA
SMB_CLK
I/O
I
Table 1. Frequency Select Pin (FSA, FSB and FSC)
FSC
0
0
0
0
1
1
1
1
FSB
0
0
1
1
0
0
1
1
FSA
0
1
0
1
0
1
0
1
CPU
266MHz
133MHz
200MHz
166MHz
333MHz
100MHz
400MHz
200MHz
100MHz
33MHz
27MHz
14.318MHz
96MHz
48MHz
SRC
PCIF/PCI
27MHz
REF
DOT96
USB
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CKPWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CKPWRGD and indicates that VTT voltage is stable then FSA,
FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CKPWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CKPWRGD transitions are ignored except in test mode.
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in
Table 2.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
.
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
.........................DOC #: SP-AP-0021 (Rev AA) Page 4 of 28
SL28506
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
Slave address–7 bits
Read = 1
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
.........................DOC #: SP-AP-0021 (Rev AA) Page 5 of 28
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