AT25SF081
8-Mbit, 2.3V Minimum
SPI Serial Flash Memory with Dual-I/O and Quad-IO Support
Features
Single 2.3V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual and Quad Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (t
V
) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Blocks via WP Pin
3 Protected Programmable Security Register Pages
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
0.7ms Typical Page Program (256 Bytes) Time
70ms Typical 4-Kbyte Block Erase Time
300ms Typical 32-Kbyte Block Erase Time
600ms Typical 64-Kbyte Block Erase Time
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
2µA Deep Power-Down Current (Typical)
10µA Standby current (Typical)
4mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil and 208-mil)
8-pad Ultra Thin DFN (5 x 6 x 0.6 mm and 2 x 3 x 0.6 mm)
8-lead TSSOP (4 x 4 mm)
Die in Wafer Form
DS-25SF081–045I–8/2017
Description
The Adesto
®
AT25SF081 is a serial interface Flash memory device designed for use in a wide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM
for execution. The flexible erase architecture of the AT25SF081 is ideal for data storage as well, eliminating the need for
additional data storage devices.
The erase block sizes of the AT25SF081 have been optimized to meet the needs of today's code and data storage
applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because
certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and
unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased
memory space efficiency allows additional code routines and data storage segments to be added while still maintaining
the same overall device density.
The device also contains three pages of Security Register that can be used for purposes such as unique device
serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. These Security Register
pages can be individually locked.
1.
Pin Descriptions and Pinouts
Pin Descriptions
Name and Function
CHIP SELECT:
Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down
mode), and the SO pin will be in a high-impedance state. When the device is deselected,
data will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
SERIAL CLOCK:
This pin is used to provide a clock to the device and is used to control the
flow of data to and from the device. Command, address, and input data present on the SI pin
is always latched in on the rising edge of SCK, while output data on the SO pin is always
clocked out on the falling edge of SCK.
SERIAL INPUT:
The SI pin is used to shift data into the device. The SI pin is used for all data
input including command and address sequences. Data on the SI pin is always latched in on
the rising edge of SCK.
With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output pin
(I/O
0
) in conjunction with other pins to allow two or four bits of data on (I/O
3-0
) to be clocked
in on every falling edge of SCK
To maintain consistency with the SPI nomenclature, the SI (I/O
0
) pin will be referenced as
the SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it
will be referenced as I/O
0
Data present on the SI pin will be ignored whenever the device is deselected (CS is
deasserted).
Asserted
State
Type
Table 1-1.
Symbol
CS
Low
Input
SCK
-
Input
SI (I/O
0
)
-
Input/Output
AT25SF081
DS-25SF081–045I–8/2017
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Table 1-1.
Symbol
Pin Descriptions (Continued)
Name and Function
SERIAL OUTPUT:
The SO pin is used to shift data out from the device. Data on the SO pin
is always clocked out on the falling edge of SCK.
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O
0
) in
conjunction with other pins to allow two bits of data on (I/O
1-0
) to be clocked in on every
falling edge of SCK
To maintain consistency with the SPI nomenclature, the SO (I/O
1
) pin will be referenced as
the SO pin unless specifically addressing the Dual-I/O modes in which case it will be
referenced as I/O
1
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
WRITE PROTECT:
The WP pin controls the hardware locking feature of the device. With the
Quad-Output Read commands, the WP Pin becomes an output pin (I/O
2
) in conjunction with
other pins to allow four bits of data on (I/O3
3-0
) to be clocked in on every falling edge of SCK.
Asserted
State
Type
SO (I/O
1
)
-
Input/Output
WP
(I/O
2
)
To maintain consistency with the SPI nomenclature, the WP (I/O
2
) pin will be referenced as
the WP pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O
2
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected
to V
CC
whenever possible.
HOLD:
The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK
pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold Function” on page 31
for additional details on the Hold operation.
With the Quad-Output Read commands, the HOLD Pin becomes an output pin (I/O
3
) in
conjunction with other pins to allow four bits of data on (I/O3
3-0
) to be clocked in on every
falling edge of SCK.
To maintain consistency with the SPI nomenclature, the HOLD (I/O
3
) pin will be referenced
as the HOLD pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O
3
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be
used. However, it is recommended that the HOLD pin also be externally connected to V
CC
whenever possible.
DEVICE POWER SUPPLY:
The V
CC
pin is used to supply the source voltage to the device.
-
Input/Output
HOLD
(I/O
3
)
-
Input/Output
V
CC
Operations at invalid V
CC
voltages may produce spurious results and should not be
attempted.
GROUND:
The ground reference for the power supply. GND should be connected to the
system ground.
-
Power
GND
-
Power
AT25SF081
DS-25SF081–045I–8/2017
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Figure 1-1. 8-SOIC, 8-TSSOP (Top View)
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Figure 1-2. 8-UDFN (Top View)
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
2.
Block Diagram
Figure 2-1. Block Diagram
CS
Control and
Protection Logic
I/O Buffers
and Latches
SRAM
Data Buffer
SCK
SI (I/O0)
SO (I/O1)
Interface
Control
And
Logic
Address Latch
Y-Decoder
Y-Gating
WP (I/O2)
HOLD (I/O3)
X-Decoder
Flash
Memory
Array
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.
3.
Memory Array
To provide the greatest flexibility, the memory array of the AT25SF081 can be erased in four levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
AT25SF081
DS-25SF081–045I–8/2017
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Figure 3-1. Memory Architecture Diagram
Block Erase Detail
64KB
32KB
4KB
Block Address
Range
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
•••
0FFFFFh–0FF000h
0FEFFFh–0FE000h
0FDFFFh–0FD000h
0FCFFFh–0FC000h
0FBFFFh–0FB000h
0FAFFFh–0FA000h
0F9FFFh–0F9000h
0F8FFFh–0F8000h
0F7FFFh–0F7000h
0F6FFFh–0F6000h
0F5FFFh–0F5000h
0F4FFFh–0F4000h
0F3FFFh–0F3000h
0F2FFFh–0F2000h
0F1FFFh–0F1000h
0F0FFFh–0F0000h
0EFFFFh–0EF000h
0EEFFFh–0EE000h
0EDFFFh–0ED000h
0ECFFFh–0EC000h
0EBFFFh–0EB000h
0EAFFFh–0EA000h
0E9FFFh–0E9000h
0E8FFFh–0E8000h
0E7FFF
h–0
E7000h
0E6FFF
h–0
E6000h
0E5FFF
h–0
E5000h
0E4FFFh–0E4000h
0E3FFFh–0E3000h
0E2FFFh–0E2000h
0E1FFFh–0E1000h
0E0FFFh–0E0000h
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
•••
Page Program Detail
1-256 Byte
Page Address
Range
0FFFFFh–0FFF00h
0FFEFFh–0FFE00h
0FFDFFh–0FFD00h
0FFCFFh–0FFC00h
0FFBFFh–0FFB00h
0FFAFFh–0FFA00h
0FF9FFh–0FF900h
0FF8FFh–0FF800h
0FF7FFh–0FF700h
0FF6FFh–0FF600h
0FF5FFh–0FF500h
0FF4FFh–0FF400h
0FF3FFh–0FF300h
0FF2FFh–0FF200h
0FF1FFh–0FF100h
0FF0FFh–0FF000h
0FEFFFh–0FEF00h
0FEEFFh–0FEE00h
0FEDFFh–0FED00h
0FECFFh–0FEC00h
0FEBFFh–0FEB00h
0FEAFFh–0FEA00h
0FE9FFh–0FE900h
0FE8FFh–0FE800h
32KB
64KB
Sector 15
32KB
32KB
64KB
Sector 14
32KB
32KB
64KB
Sector 0
32KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
00FFFFh–00F000h
00EFFFh–00E000h
00DFFFh–00D000h
00CFFFh–00C000h
00BFFFh–00B000h
00AFFFh–00A000h
009FFFh–009000h
008FFFh–008000h
007FFFh–007000h
006FFFh–006000h
005FFFh–005000h
004FFFh–004000h
003FFFh–003000h
002FFFh–002000h
001FFFh–001000h
000FFFh–000000h
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
0017FFh–001700h
0016FFh–001600h
0015FFh–001500h
0014FFh–001400h
0013FFh–001300h
0012FFh–001200h
0011FFh–001100h
0010FFh–001000h
000FFFh–000F00h
000EFFh–000E00h
000DFFh–000D00h
000CFFh–000C00h
000BFFh–000B00h
000AFFh–000A00h
0009FFh–000900h
0008FFh–000800h
0007FFh–000700h
0006FFh–000600h
0005FFh–000500h
0004FFh–000400h
0003FFh–000300h
0002FFh–000200h
0001FFh–000100h
0000FFh–000000h
•••
•••
AT25SF081
DS-25SF081–045I–8/2017
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