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M52S128168A-7.5BIG

Description
Synchronous DRAM, 4MX16, 6ns, CMOS, PBGA54, 8 X 8 MM, LEAD FREE, VFBGA-54
Categorystorage   
File Size1MB,47 Pages
ManufacturerESMT
Websitehttp://www.esmt.com.tw/
Elite Semiconductor Memory Technology Inc. (ESMT) is a professional IC design company founded by Dr. Hu Zhao in June 1998. Its headquarters is located in Hsinchu Science Park, Taiwan. The company's main business includes research, development, manufacturing, sales and related technical services of IC products. It was listed on the Taiwan Stock Exchange in March 2002.
Download Datasheet Parametric View All

M52S128168A-7.5BIG Overview

Synchronous DRAM, 4MX16, 6ns, CMOS, PBGA54, 8 X 8 MM, LEAD FREE, VFBGA-54

M52S128168A-7.5BIG Parametric

Parameter NameAttribute value
MakerESMT
Parts packaging codeBGA
package instructionVFBGA,
Contacts54
Reach Compliance Codeunknown
ECCN codeEAR99
Is SamacsysN
access modeFOUR BANK PAGE BURST
Maximum access time6 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeS-PBGA-B54
length8 mm
memory density67108864 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals54
word count4194304 words
character code4000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize4MX16
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Package shapeSQUARE
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
Certification statusNot Qualified
Maximum seat height1 mm
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
width8 mm
Base Number Matches1

M52S128168A-7.5BIG Preview

Download Datasheet
ESMT
Mobile SDRAM
FEATURES
2.5V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
EMRS cycle with address
All inputs are sampled at the positive going edge of the
system clock
Special function support
-
PASR (Partial Array Self Refresh)
-
TCSR (Temperature Compensated Self Refresh)
-
DS (Driver Strength)
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
M52S128168A
Operation Temperature Condition -40
°
C~85
°
C
2M x 16 Bit x 4 Banks
Synchronous DRAM
ORDERING INFORMATION
Product ID
M52S128168A-7TIG
M52S128168A-7BIG
M52S128168A-7.5TIG
M52S128168A-7.5BIG
M52S128168A-10TIG
M52S128168A-10BIG
Max Freq.
143MHz
143MHz
133MHz
133MHz
100MHz
100MHz
Package
54 TSOP II
54 Ball FBGA
54 TSOP II
54 Ball FBGA
54 TSOP II
54 Ball FBGA
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The M52S128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words
by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT (Top View)
1
2
DQ15
3
VSSQ
4
5
6
7
VDDQ
8
DQ0
9
VDD
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
A
VSS
B
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
C
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS
RAS
WE
G
NC
A11
A9
BA0
BA1
CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
54 Ball FBGA
(8x8mm)
(mm ball pitch)
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2008
Revision: 1.0
1/47

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