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M13S64164A-6TG2Y

Description
DDR DRAM, 4MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66
Categorystorage   
File Size1MB,49 Pages
ManufacturerESMT
Websitehttp://www.esmt.com.tw/
Elite Semiconductor Memory Technology Inc. (ESMT) is a professional IC design company founded by Dr. Hu Zhao in June 1998. Its headquarters is located in Hsinchu Science Park, Taiwan. The company's main business includes research, development, manufacturing, sales and related technical services of IC products. It was listed on the Taiwan Stock Exchange in March 2002.
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M13S64164A-6TG2Y Overview

DDR DRAM, 4MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66

M13S64164A-6TG2Y Parametric

Parameter NameAttribute value
MakerESMT
package instructionTSOP2,
Reach Compliance Codeunknown
Is SamacsysN
access modeFOUR BANK PAGE BURST
Maximum access time0.7 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PDSO-G66
length22.22 mm
memory density67108864 bit
Memory IC TypeDDR DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals66
word count4194304 words
character code4000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4MX16
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Maximum seat height1.2 mm
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width10.16 mm
Base Number Matches1

M13S64164A-6TG2Y Preview

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ESMT
DDR SDRAM
Features
Double-data-rate architecture, two data transfers per clock cycle
Bi-directional data strobe (DQS)
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Four bank operation
CAS Latency : 2, 2.5, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
M13S64164A (2Y)
1M x 16 Bit x 4 Banks
Double Data Rate SDRAM
All inputs except data & DM are sampled at the rising edge of the system clock (CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
Data mask (DM) for write masking only
V
DD
= 2.5V
±
0.2V, V
DDQ
= 2.5V
±
0.2V
15.6us refresh interval
Auto & Self refresh
2.5V I/O (SSTL_2 compatible)
Ordering Information
Product ID
M13S64164A-4TG2Y
M13S64164A-5TG2Y
M13S64164A-6TG2Y
M13S64164A-4BG2Y
M13S64164A-5BG2Y
M13S64164A-6BG2Y
Max Freq.
250MHz (DDR500)
200MHz (DDR400)
166MHz (DDR333)
250MHz (DDR500)
200MHz (DDR400)
166MHz (DDR333)
60 Ball BGA
Pb-free
66 pin TSOPII
Package
Comments
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2012
Revision : 1.0
1/49
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