DSPIC33EP16GS504-I/PT datasheet, PDF

dsPIC33EPXXGS50X FAMILY

16-Bit Digital Signal Controllers for Digital Power Applications with

Interconnected High-Speed PWM, ADC, PGA and Comparators

Operating Conditions

• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS

• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS

Advanced Analog Features

• High-Speed ADC module:

- 12-bit with 4 dedicated SAR ADC cores and

one shared SAR ADC core

- Configurable resolution (up to 12-bit) for each

ADC core

- Up to 3.25 Msps conversion rate per channel

at 12-bit resolution

- 12 to 22 single-ended inputs

- Dedicated result buffer for each analog channel

- Flexible and independent ADC trigger sources

- Two digital comparators

- Two oversampling filters for increased

resolution

• Four Rail-to-Rail Comparators with Hysteresis:

- Dedicated 12-bit Digital-to-Analog Converter

(DAC) for each analog comparator

- Up to two DAC reference outputs

- Up to two external reference inputs

• Two Programmable Gain Amplifiers:

- Single-ended or independent ground reference

- Five selectable gains (4x, 8x, 16x, 32x and 64x)

- 40 MHz gain bandwidth

Flash Architecture

• Dual Partition Flash Program Memory with

Live Update (64-Kbyte devices):

- Supports programming while operating

- Supports partition soft swap

Core: 16-Bit dsPIC33E CPU

Code-Efficient (C and Assembly) Architecture

Two 40-Bit Wide Accumulators

Single-Cycle (MAC/MPY) with Dual Data Fetch

Single-Cycle Mixed-Sign MUL Plus

Hardware Divide

• 32-Bit Multiply Support

• Two Additional Working Register Sets (reduces

context switching)

•

Clock Management

•

±0.9% Internal Oscillator

Programmable PLLs and Oscillator Clock Sources

Fail-Safe Clock Monitor (FSCM)

Independent Watchdog Timer (WDT)

Fast Wake-up and Start-up

Interconnected SMPS Peripherals

• Reduces CPU Interaction to Improve Performance

• Flexible PWM Trigger Options for

ADC Conversions

• High-Speed Comparator Truncates PWM

(15 ns typical):

- Supports Cycle-by-Cycle Current mode control

- Current Reset mode (variable frequency)

Power Management

• Low-Power Management modes (Sleep,

Idle, Doze)

• Integrated Power-on Reset and Brown-out Reset

• 0.5 mA/MHz Dynamic Current (typical)

• 10

μA

I

PD

Current (typical)

High-Speed PWM

• Five PWM Generators (two outputs per generator)

• Individual Time Base and Duty Cycle for each PWM

• 1.04 ns PWM Resolution (frequency, duty cycle,

dead time and phase)

• Supports Center-Aligned, Redundant, Complementary

and True Independent Output modes

• Independent Fault and Current-Limit Inputs

• Output Override Control

• PWM Support for AC/DC, DC/DC, Inverters, PFC

and Lighting

Timers/Output Compare/Input Capture

• Five 16-Bit and up to Two 32-Bit Timers/Counters

• Four Output Compare (OC) modules, Configurable

as Timers/Counters

• Four Input Capture (IC) modules



2013-2015 Microchip Technology Inc.

DS70005127C-page 1

dsPIC33EPXXGS50X FAMILY

Communication Interfaces

• Two UART modules (15 Mbps):

- Supports LIN/J2602 protocols and IrDA

®

• Two 4-Wire SPI modules (15 Mbps)

• Two I

2

C modules (up to 1 Mbaud) with SMBus

Support

Qualification and Class B Support

• AEC-Q100 REVG (Grade 1, -40°C to +125°C)

• Class B Safety Library, IEC 60730

• The 6x6x0.5 mm UQFN Package is Designed and

Optimized to ease IPC9592B 2nd Level

Temperature Cycle Qualification

Input/Output

• Constant-Current Source (10 µA nominal)

• Sink/Source up to 12mA/15mA, respectively;

Pin-Specific for Standard V

OH

/V

OL

• 5V Tolerant Pins

• Selectable, Open-Drain Pull-ups and Pull-Downs

• External Interrupts on All I/O Pins

• Peripheral Pin Select (PPS) to allow Function

Remap with Six Virtual I/Os

Debugger Development Support

• In-Circuit and In-Application Programming

• Five Program and Three Complex

Data Breakpoints

• IEEE 1149.2 Compatible (JTAG) Boundary Scan

• Trace and Run-Time Watch

General Purpose I/O (GPIO)

External Interrupts

(3)

Constant-Current Source

1

Program Memory Bytes

Remappable Peripherals

Analog Comparator

12-Bit

ADC

Reference Clock

RAM (Bytes)

DAC Output

Output Compare

Input Capture

Analog Inputs

S&H Circuits

Timers

(1)

dsPIC33EP16GS502

dsPIC33EP32GS502

dsPIC33EP64GS502

dsPIC33EP16GS504

dsPIC33EP32GS504

dsPIC33EP64GS504

dsPIC33EP16GS505

dsPIC33EP32GS505

dsPIC33EP64GS505

dsPIC33EP16GS506

dsPIC33EP32GS506

dsPIC33EP64GS506

Note 1:

2:

3:

28

44

48

64

16K

32K

64K

16K

32K

64K

16K

32K

64K

16K

32K

64K

2K

4K

8K

2K

4K

8K

2K

4K

8K

2K

4K

8K

21

35

53

5

4

2

5x2

PWM

(2)

UART

Device

SPI

3

4

1

2

12

19

22

5

2

4

1

2

SOIC,

QFN-S,

UQFN

QFN,

TQFP

The external clock for Timer1, Timer2 and Timer3 is remappable.

PWM4 and PWM5 are remappable on all devices except the 64-pin devices.

External interrupts, INT0 and INT4, are not remappable.

DS70005127C-page 2



2013-2015 Microchip Technology Inc.

Packages

PGA

Pins

I

2

C

dsPIC33EPXXGS50X FAMILY

Pin Diagrams

28-Pin SOIC

MCLR

RA0

RA1

RA2

RB0

RB9

RB10

V

SS

RB1

RB2

RB3

RB4

V

DD

RB8

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AV

DD

AV

SS

RA3

RA4

RB14

RB13

RB12

RB11

V

CAP

V

SS

RB7

RB6

RB5

RB15

dsPIC33EPXXGS502

1

2

3

4

5

6

7

8

9

10

11

12

13

14

MCLR

Pin Function

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Pin Function

PGEC3/SCL2/RP47/RB15

TDO/AN19/PGA2N2/RP37/RB5

PGED1/TDI/AN20/SCL1/RP38/RB6

PGEC1/AN21/SDA1/RP39/RB7

V

SS

V

CAP

TMS/PWM3H/RP43/RB11

TCK/PWM3L/RP44/RB12

PWM2H/RP45/RB13

PWM2L/RP46/RB14

PWM1H/RA4

PWM1L/RA3

AV

SS

AV

DD

AN0/PGA1P1/CMP1A/RA0

AN1/PGA1P2/PGA2P1/CMP1B/RA1

AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2

AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0

AN4/CMP2C/CMP3A/ISRC4/RP41/RB9

AN5/CMP2D/CMP3B/ISRC3/RP42/RB10

Vss

OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1

OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2

PGED2/AN18/DACOUT1/INT0/RP35/RB3

PGEC2/ADTRG31/EXTREF1/RP36/RB4

V

DD

PGED3/SDA2/RP40/RB8

Legend: Shaded pins

are up to 5 VDC tolerant.

RPn

represents remappable peripheral functions. See

Table 10-1

and

Table 10-2

for the complete list of remappable sources.



2013-2015 Microchip Technology Inc.

DS70005127C-page 3

dsPIC33EPXXGS50X FAMILY

Pin Diagrams (Continued)

28-Pin QFN-S, UQFN

MCLR

AV

DD

AV

SS

RA1

RA0

RA3

28

27

26

25

24

23

RA2

RB0

RB9

RB10

V

SS

RB1

RB2

1

2

3

4

5

6

7

10

12

13

14

11

8

9

22

21

20

19

RA4

RB14

RB13

RB12

RB11

V

CAP

V

SS

RB7

dsPIC33EPXXGS502

18

17

16

15

RB3

RB4

RB8

RB5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Pin Function

AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2

AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0

AN4/CMP2C/CMP3A/ISRC4/RP41/RB9

AN5/CMP2D/CMP3B/ISRC3/RP42/RB10

Vss

OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1

OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2

PGED2/AN18/DACOUT1/INT0/RP35/RB3

PGEC2/ADTRG31/EXTREF1/RP36/RB4

V

DD

PGED3/SDA2/RP40/RB8

PGEC3/SCL2/RP47/RB15

TDO/AN19/PGA2N2/RP37/RB5

PGED1/TDI/AN20/SCL1/RP38/RB6

RB15

15

16

17

18

19

20

21

22

23

24

25

26

27

28

RB6

V

DD

Pin Function

PGEC1/AN21/SDA1/RP39/RB7

V

SS

V

CAP

TMS/PWM3H/RP43/RB11

TCK/PWM3L/RP44/RB12

PWM2H/RP45/RB13

PWM2L/RP46/RB14

PWM1H/RA4

PWM1L/RA3

AV

SS

AV

DD

MCLR

AN0/PGA1P1/CMP1A/RA0

AN1/PGA1P2/PGA2P1/CMP1B/RA1

Legend: Shaded pins

are up to 5 VDC tolerant.

RPn

represents remappable peripheral functions. See

Table 10-1

and

Table 10-2

for the complete list of remappable sources.

DS70005127C-page 4



2013-2015 Microchip Technology Inc.

dsPIC33EPXXGS50X FAMILY

Pin Diagrams (Continued)

44-Pin QFN

RB15

RC8

RC7

RC2

36

RB6

RB5

RB8

RB4

35

44

43

42

41

40

39

38

37

RB7

RC4

RC5

RC6

RC3

V

SS

V

CAP

RB11

RB12

RB13

RB14

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

34

33

32

31

30

29

28

27

26

25

24

23

RB3

V

DD

V

SS

RB2

RB1

RC1

V

SS

V

DD

RC10

RC9

RB10

RB9

RB0

RA2

dsPIC33EPXXGS504

RA0

RA4

RA3

RC0

RC11

RC13

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

AN1ALT/RP52/RC4

AN0ALT/RP53/RC5

AN17/RP54/RC6

RP51/RC3

V

SS

V

CAP

Pin Function

PGEC1/AN21/SDA1/RP39/RB7

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

MCLR

RC12

AV

DD

AV

SS

RA1

Pin Function

AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2

AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0

AN4/CMP2C/CMP3A/ISRC4/RP41/RB9

AN5/CMP2D/CMP3B/ISRC3/RP42/RB10

AN11/PGA1N3/RP57/RC9

AN10/PGA1P4/EXTREF2/RP58/RC10

V

DD

V

SS

AN8/PGA2P4/CMP4C/RP49/RC1

OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1

OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2

PGED2/AN18/DACOUT1/INT0/RP35/RB3

PGEC2/ADTRG31/RP36/RB4

AN9/CMP4D/EXTREF1/RP50 /RC2

ASDA1/RP55/RC7

ASCL1/RP56/RC8

V

SS

V

DD

PGED3/SDA2/RP40/RB8

PGEC3/SCL2/RP47/RB15

TDO/AN19/PGA2N2/RP37/RB5

PGED1/TDI/AN20/SCL1/RP38/RB6

TMS/PWM3H/RP43/RB11

TCK/PWM3L/RP44/RB12

PWM2H/RP45/RB13

PWM2L/RP46/RB14

PWM1H/RA4

PWM1L/RA3

FLT12/RP48/RC0

FLT11/RP61/RC13

AV

SS

AV

DD

MCLR

AN12/ISRC1/RP59/RC11

AN14/PGA2N3/RP60/RC12

AN0/PGA1P1/CMP1A/RA0

AN1/PGA1P2/PGA2P1/CMP1B/RA1

Legend: Shaded pins

are up to 5 VDC tolerant.

RPn

represents remappable peripheral functions. See

Table 10-1

and

Table 10-2

for the complete list of remappable sources.



2013-2015 Microchip Technology Inc.

DS70005127C-page 5

Parameter Name	Attribute value
core processor	dsPIC
core size	16-bit
speed	70 MIPs
Connectivity	I²C，IrDA，LINbus，SPI，UART/USART
Peripheral	Undervoltage detection/reset, POR, PWM, WDT
Number of I/Os	35
Program storage capacity	16KB（16K x 8）
Program memory type	flash memory
EEPROM capacity	-
RAM capacity	2K x 8
Voltage - Power Supply (Vcc/Vdd)	3 V ~ 3.6 V
data converter	A/D 19x12b，D/A 1x12b
Oscillator type	internal
Operating temperature	-40°C ~ 85°C（TA）
Package/casing	44-TQFP
Supplier device packaging	44-TQFP（10x10）

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