White Electronic Designs
512Kx32 SRAM 3.3V MULTICHIP PACKAGE
FEATURES
Access Times of 15, 17, 20ns
Low Voltage Operation
Packaging
• 66-pin, PGA Type, 1.075 inch square, Hermetic
Ceramic HIP (Package 400)
• 68 lead, 22.4mm (0.880 inch) CQFP, (G2U),
3.56mm (0.140"), (Package 510)
Organized as 512Kx32; User Configurable as
2x512Kx16 or 4x512Kx8
Commercial, Industrial and Military Temperature
Ranges
Low Voltage Operation:
• 3.3V ± 10% Power Supply
Low Power CMOS
WS512K32V-XXX
TTL Compatible Inputs and Outputs
Fully Static Operation:
• No clock or refresh required.
Three State Output.
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight
WS512K32V-XG2UX - 8 grams typical
WS512K32NV-XH1X - 13 grams typical
* This product is subject to change without notice.
PIN CONFIGURATION FOR WS512K32NV-XH1X
Top View
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
A
17
I/O
0
I/O
1
I/O
2
11
22
12
WE
2
#
CS
2
#
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
#
NC
I/O
3
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE#
A
18
WE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
#
WE
4
#
I/O
27
A
3
A
4
A
5
WE
3
#
CS
3
#
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
8
8
8
8
OE#
A
0-18
WE
1
# CS
1
#
Pin Description
56
I/O
0-31
A
0-18
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
Block Diagram
WE
2
# CS
2
#
WE
3
# CS
3
#
WE
4
# CS
4
#
512K x 8
512K x 8
512K x 8
512K x 8
I/O
20
66
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
March 2006
Rev. 12
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATION FOR WS512K32V-XG2UX
Top View
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
#
GND
CS
4
#
WE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
WS512K32V-XXX
Pin Description
I/O
0-31
A
0-18
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
#
OE#
CS
2
#
A
17
WE
2
#
WE
3
#
WE
4
#
A
18
NC
NC
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
Block Diagram
WE
1
# CS
1
#
WE
2
# CS
2
#
WE
3
# CS
3
#
WE
4
# CS
4
#
OE#
A
0-18
512K x 8
512K x 8
512K x 8
512K x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
March 2006
Rev. 12
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
4.6
150
4.6
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
X
H
WE
X
H
L
H
WS512K32V-XXX
TRUTH TABLE
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
IH
V
IL
Min
3.0
2.2
-0.3
Max
3.6
V
CC
+ 0.3
+0.8
Unit
V
V
V
CAPACITANCE
T
A
= +25°C
Parameter
OE# capacitance
WE
1-4
# capacitance
HIP (PGA)
CQFP G2U
CS
1-4
# capacitance
Data# I/O capacitance
Address input capacitance
Symbol
Conditions
C
OE
V
IN
= 0V, f = 1.0 MHz
C
WE
V
IN
= 0V, f = 1.0 MHz
Max Unit
50 pF
pF
20
20
V
IN
= 0V, f = 1.0 MHz 20 pF
V
I/O
= 0V, f = 1.0 MHz 20 pF
V
IN
= 0V, f = 1.0 MHz 50 pF
C
CS
C
I/O
C
AD
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 3.3V ± 0.3V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Sym
I
LI
I
LO
I
CC
x 32
I
SB
V
OL
V
OH
Conditions
Min
V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 3.6
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 3.6
I
OL
= 4.0mA
I
OH
= -4.0mA
Units
Max
10
10
400
200
0.4
2.4
µA
µA
mA
mA
V
V
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V.
Contact factory for low power option.
March 2006
Rev. 12
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
AC CHARACTERISTICS
V
CC
= 3.3V, GND = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
t
OLZ
1
t
CHZ
1
t
OHZ
1
Min
15
0
15
8
1
0
8
8
1
0
8
8
-15
Max
15
0
17
8
Min
17
-17
Max
17
WS512K32V-XXX
-20
Min
20
0
20
10
1
0
10
10
Max
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
V
CC
= 3.3V, GND = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
t
WHZ
1
t
DH
Min
15
12
12
9
12
0
0
2
0
-15
Max
Min
17
12
12
9
14
0
0
3
0
-17
Max
Min
20
14
14
10
14
0
0
3
0
-20
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
8
8
9
1. This parameter is guaranteed by design but not tested.
AC TEST CIRCUIT
AC Test Conditions
I
OL
Current Source
D.U.T.
C
eff
= 50 pf
V
Z
≈
1.5V
(Bipolar Supply)
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 2.5
5
1.5
1.5
Unit
V
ns
V
V
I
OH
Current Source
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
March 2006
Rev. 12
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
TIMING WAVEFORM - READ CYCLE
WS512K32V-XXX
t
RC
ADDRESS
t
AA
t
RC
ADDRESS
CS#
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
ACS
t
CLZ
OE#
t
CHZ
READ CYCLE 1 (CS# = OE# = V
IL
, WE# = V
IH
)
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
t
OHZ
DATA VALID
READ CYCLE 2 (WE# = V
IH
)
WRITE CYCLE - WE# CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
CS#
t
AH
t
AS
WE#
t
WP
t
OW
t
WHZ
t
DW
DATA VALID
t
DH
DATA I/O
WRITE CYCLE 1, WE# CONTROLLED
WRITE CYCLE - CS# CONTROLLED
t
WC
ADDRESS
WS32K32-XHX
t
CW
t
AH
t
AS
CS#
t
AW
t
WP
WE#
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, CS# CONTROLLED
March 2006
Rev. 12
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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