1550 MHz to 2650 MHz Quadrature Modulator with
2100 MHz to 2600 MHz Frac-N PLL and Integrated VCO
Data Sheet
FEATURES
IQ modulator with integrated fractional-N PLL
RF output frequency range: 1550 MHz to 2650 MHz
Internal LO frequency range: 2100 MHz to 2600 MHz
Output P1dB: 14.2 dBm @ 2140 MHz
Output IP3: 33.2 dBm @ 2140 MHz
Noise floor: −159.6 dBm/Hz @ 2140 MHz
Baseband bandwidth: 750 MHz (3 dB)
SPI serial interface for PLL programming
Integrated LDOs and LO buffer
Power supply: 5 V/240 mA
40-lead 6 mm × 6 mm LFCSP
ADRF6703
The integrated fractional-N PLL/synthesizer generates a 2× f
LO
input to the IQ modulator. The phase detector together with an
external loop filter is used to control the VCO output. The VCO
output is applied to a quadrature divider. To reduce spurious
components, a sigma-delta (Σ-Δ) modulator controls the
programmable PLL divider.
The IQ modulator has wideband differential I and Q inputs,
which support baseband as well as complex IF architectures.
The single-ended modulator output is designed to drive a
50 Ω load impedance and can be disabled.
The
ADRF6703
is fabricated using an advanced silicon-
germanium BiCMOS process. It is available in a 40-lead,
exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP package.
Performance is specified from −40°C to +85°C. A lead-free
evaluation board is available.
Table 1.
Part No.
ADRF6701
ADRF6702
ADRF6703
ADRF6704
Internal LO Range
750 MHz
1150 MHz
1550 MHz
2150 MHz
2100 MHz
2600 MHz
2500 MHz
290 MHz
±3 dB RF
OUT
Balun Range
400 MHz
1250 MHz
1200 MHz
2400 MHz
1550 MHz
2650 MHz
2050 MHz
3000 MHz
APPLICATIONS
Cellular communications systems
GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA, LTE
Broadband wireless access systems
Satellite modems
GENERAL DESCRIPTION
The
ADRF6703
provides a quadrature modulator and
synthesizer solution within a small 6 mm × 6 mm footprint
while requiring minimal external components.
The
ADRF6703
is designed for RF outputs from 1550 MHz to
2650 MHz. The low phase noise VCO and high performance
quadrature modulator make the
ADRF6703
suitable for next
generation communication systems requiring high signal
dynamic range and linearity. The integration of the IQ
modulator, PLL, and VCO provides for significant board
savings and reduces the BOM and design complexity.
VCC7
34
FUNCTIONAL BLOCK DIAGRAM
VCC6
29
VCC5
27
VCC4
22
VCC3
17
VCC2
10
VCC1
1
LOSEL
36
LON
37
BUFFER
ADRF6703
DIVIDER
÷2
2:1
MUX
40
DECL3
9
2
LOP
38
BUFFER
DECL2
DECL1
DATA
12
CLK
13
LE
14
SPI
INTERFACE
FRACTION
REG
MODULUS
INTEGER
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
×2
N COUNTER
21 TO 123
MUX
TEMP
SENSOR
4
7
REFIN
6
PRESCALER
÷2
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
24
5
3
VCO
CORE
18
QP
÷2
0/90
19
QN
32
IN
33
IP
÷2
÷4
MUXOUT
8
–
PHASE
+ FREQUENCY
DETECTOR
11 15 20 21 23 25 28 30 31 35
39
16
26
08570-001
GND
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
NC
RSET
CP VTUNE ENOP RFOUT
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADRF6703
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 16
PLL + VCO .................................................................................. 16
Basic Connections for Operation ............................................. 16
External LO ................................................................................. 16
Loop Filter ................................................................................... 17
DAC-to-IQ Modulator Interfacing .......................................... 18
Adding a Swing-Limiting Resistor ........................................... 18
IQ Filtering .................................................................................. 19
Baseband Bandwidth ................................................................. 19
Data Sheet
Device Programming and Register Sequencing..................... 19
Register Summary .......................................................................... 20
Register Description....................................................................... 21
Register 0—Integer Divide Control (Default: 0x0001C0) .... 21
Register 1—Modulus Divide Control (Default: 0x003001) .. 22
Register 2—Fractional Divide Control (Default: 0x001802) 22
Register 3—Σ-Δ Modulator Dither Control (Default:
0x10000B) .................................................................................... 23
Register 4—PLL Charge Pump, PFD, and Reference Path
Control (Default: 0x0AA7E4)................................................... 24
Register 5—LO Path and Modulator Control (Default:
0x0000D5) ................................................................................... 26
Register 6—VCO Control and VCO Enable (Default:
0x1E2106) .................................................................................... 27
Register 7—External VCO Enable ........................................... 27
Characterization Setups ................................................................. 28
Evaluation Board ............................................................................ 30
Evaluation Board Control Software ......................................... 30
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
REVISION HISTORY
10/11—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 1
6/11—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Figure 5 ........................................................................ 10
Changes to Figure 17 and Figure 18 ............................................. 12
6/11—Revision 0: Initial Version
Rev. B | Page 2 of 36
Data Sheet
SPECIFICATIONS
ADRF6703
V
S
= 5 V; T
A
= 25°C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q
frequency (f
BB
) = 1 MHz; f
PFD
= 38.4 MHz; f
REF
= 153.6 MHz at +4 dBm Re:50 Ω (1 V p-p); 130 kHz loop filter, unless otherwise noted.
Table 2.
Parameter
OPERATING FREQUENCY RANGE
RF OUTPUT = 2140 MHz
Nominal Output Power
IQ Modulator Voltage Gain
OP1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
RF OUTPUT = 2300 MHz
Nominal Output Power
IQ Modulator Voltage Gain
OP1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
RF OUTPUT = 2600 MHz
Nominal Output Power
IQ Modulator Voltage Gain
OP1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
SYNTHESIZER SPECIFICATIONS
Internal LO Range
Figure of Merit (FOM)
1
Test Conditions/Comments
IQ modulator (±3 dB RF output range)
PLL LO range
RFOUT pin
Baseband VIQ = 1 V p-p differential
RF output divided by baseband input voltage
Min
1550
2100
4.95
0.95
14.2
−44.1
−52.3
+0.0/−0.6
0.04
−63.0
−52.0
70.1
33.2
−159.6
4.48
0.48
13.5
−46.0
−44.0
−0.25/−0.98
0.06
−67.0
−53.0
68.6
32.7
−159.7
2.75
−1.25
11.8
−46.8
−35.3
0.56/2.3
0.06
−63.0
−51.0
62.0
29.2
−161.7
2100
−222.0
2600
Typ
Max
2650
2600
Unit
MHz
MHz
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
MHz
dBc/Hz/Hz
P
OUT
− P (f
LO
± (2 × f
BB
))
P
OUT
− P (f
LO
± (3 × f
BB
))
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
≈ −2 dBm per tone
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
≈ −2 dBm per tone
I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset
RFOUT pin
Baseband VIQ = 1 V p-p differential
RF output divided by baseband input voltage
P
OUT
− P (f
LO
± (2 × f
BB
))
P
OUT
− P (f
LO
± (3 × f
BB
))
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
≈ −2 dBm per tone
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
≈ −2 dBm per tone
I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset
RFOUT pin
Baseband VIQ = 1 V p-p differential
RF output divided by baseband input voltage
P
OUT
− P (f
LO
± (2 × f
BB
))
P
OUT
− P (f
LO
± (3 × f
BB
))
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
≈ −2 dBm per tone
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
≈ −2 dBm per tone)
I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset
Synthesizer specifications referenced to the modulator output
Rev. B | Page 3 of 36
ADRF6703
Parameter
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Capacitance
Phase Detector Frequency
MUXOUT Output Level
MUXOUT Duty Cycle
CHARGE PUMP
Charge Pump Current
Output Compliance Range
PHASE NOISE (FREQUENCY =
2140 MHz, f
PFD
= 38.4 MHz)
Programmable to 250 µA, 500 µA, 750 µA, 1000 µA
1
Closed loop operation (see Figure 35 for loop filter design)
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
1 kHz to 10 MHz integration bandwidth
f
PFD
/2
f
PFD
f
PFD
× 2
f
PFD
× 3
f
PFD
× 4
Closed loop operation (see Figure 35 for loop filter design)
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
1 kHz to 10 MHz integration bandwidth
f
PFD
/2
f
PFD
f
PFD
× 2
f
PFD
× 3
f
PFD
× 4
Closed loop operation (see Figure 35 for loop filter design)
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
1 kHz to 10 MHz integration bandwidth
f
PFD
/2
f
PFD
f
PFD
× 2
f
PFD
× 3
f
PFD
× 4
Measured at RFOUT, frequency = 2140 MHz
Second harmonic
Third harmonic
LOP, LON
Divide by 2 circuit in LO path enabled
Divide by 2 circuit in LO path disabled
2× LO or 1× LO mode, into a 50 Ω load, LO buffer enabled
Externally applied 2× LO, PLL disabled
Externally applied 2× LO, PLL disabled
Rev. B | Page 4 of 36
Data Sheet
Test Conditions/Comments
REFIN, MUXOUT pins
12
4
20
Low (lock detect output selected)
High (lock detect output selected)
2.7
50
500
2.8
40
0.25
160
MHz
pF
MHz
V
V
%
µA
V
Min
Typ
Max
Unit
Integrated Phase Noise
Reference Spurs
−105.3
−103.1
−127.9
−149.7
0.29
−110
−102.0
−87.2
−90.4
−98.4
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
dBc
dBc
dBc
dBc
dBc
PHASE NOISE (
FREQUENCY =
2300 MHz, f
PFD
= 38.4 MHz)
Integrated Phase Noise
Reference Spurs
−103.5
−102.2
−128.4
−149.5
0.295
−110.7
−102.3
−85.5
−92.4
−101.1
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
dBc
dBc
dBc
dBc
dBc
PHASE NOISE (
FREQUENCY =
2600 MHz, f
PFD
= 38.4 MHz)
Integrated Phase Noise
Reference Spurs
−98.8
−100.2
−129.2
−151.0
0.37
−110.6
−106.5
−88.6
−92.4
−102.5
−41
−65
2100
4200
0.1
0
50
2600
5200
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
MHz
dBm
dBm
Ω
RF OUTPUT HARMONICS
LO INPUT/OUTPUT
Output Frequency Range
LO Output Level at 2140 MHz
LO Input Level
LO Input Impedance
Data Sheet
Parameter
BASEBAND INPUTS
I and Q Input DC Bias Level
Bandwidth
Test Conditions/Comments
IP, IN, QP, QN pins
400
P
OUT
≈ −7 dBm, RF flatness of IQ modulator output calibrated out
0.5 dB
3 dB
Frequency = 1 MHz
2
Frequency = 1 MHz
2
CLK, DATA, LE, ENOP, LOSEL
1.4
0
0.1
5
VPTAT voltage measured at MUXOUT
T
A
= 25°C, RL ≥10 kΩ (LO buffer disabled)
T
A
= −40°C to +85°C, RL ≥10 kΩ
VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7
4.75
Normal Tx mode (PLL and IQMOD enabled, LO buffer disabled)
Tx mode using external LO input (internal VCO/PLL disabled)
Tx mode with LO buffer enabled
Power-down mode
1.624
3.65
5
240
134
290
22
5.25
500
350
750
945
1
3.3
0.7
600
Min
Typ
Max
ADRF6703
Unit
mV
MHz
MHz
Ω
pF
V
V
µA
pF
V
mV/°C
V
mA
mA
mA
µA
Differential Input Impedance
Differential Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INH
/I
INL
Input Capacitance, C
IN
TEMPERATURE SENSOR
Output Voltage
Temperature Coefficient
POWER SUPPLIES
Voltage Range
Supply Current
The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10log10(f
PFD
) – 20log10(f
LO
/f
PFD
). The FOM was measured across the full LO range, with f
REF
= 80 MHz,
f
REF
power = 10 dBm (500 V/μs slew rate) with a 40 MHz f
PFD
. The FOM was computed at 50 kHz offset.
2
Refer to Figure 40 for plot of input impedance over frequency.
1
Rev. B | Page 5 of 36
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