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WS1M32-17HSIA

Description
1M X 32 MULTI DEVICE SRAM MODULE, 17 ns, CQFP84
Categorystorage   
File Size149KB,8 Pages
ManufacturerETC
Download Datasheet Parametric View All

WS1M32-17HSIA Overview

1M X 32 MULTI DEVICE SRAM MODULE, 17 ns, CQFP84

WS1M32-17HSIA Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals84
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage5.5 V
Minimum supply/operating voltage4.5 V
Rated supply voltage5 V
maximum access time17 ns
Processing package description28 X 28 MM, CERAMIC, QFP-84
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeFLATPACK
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
terminal coatingGOLD
Terminal locationQUAD
Packaging MaterialsCERAMIC, METAL-SEALED COFIRED
Temperature levelCOMMERCIAL
memory width32
organize1M X 32
storage density3.36E7 deg
operating modeASYNCHRONOUS
Number of digits1.05E6 words
Number of digits1M
Spare memory width16
Memory IC typeMULTI DEVICE SRAM MODULE
serial parallelPARALLEL
White Electronic Designs
1Mx32 SRAM MODULE
FEATURES
Access Times of 17, 20, 25ns
Packaging
• 84 lead, 28mm CQFP, (Package 511)
• 66 pin PGA Type, 1.385" sq., Hermetic Ce-
ramic HIP
(Package 402)*
Organized as two banks of 512Kx32, User
Configurable as 2Mx16 or 4Mx8
* Package to be developed.
WS1M32-XXX
Commercial, Industrial and Military Temperature
Ranges
TTL Compatible Inputs and Outputs
5 Volt Power Supply
Low Power CMOS
Built-in Decoupling Caps and Multiple Ground
Pins for Low Noise Operation
Weight
WS1M32-XH2X* - 13 grams (typical)
WS1M32-XG3X - 20 grams (typical)
PIN CONFIGURATION FOR WS1M32-XH2X*
TOP VIEW
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
A
17
I/O
0
I/O
1
I/O
2
11
22
12
WE
2
OE
2
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
NC
I/O
3
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE
1
A
18
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
CS
2
A
8
A
9
I/O
16
I/O
17
I/O
18
44
34
V
CC
OE
4
WE
4
I/O
27
A
3
A
4
A
5
WE
3
OE
3
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
OE
1
W E
1
PIN DESCRIPTION
56
I/O
0
-
31
A
0-18
WE
1-4
CS
1-2
OE
1-4
V
C
C
GND
N
C
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
OE
2
W E
2
OE
3
W E
3
OE
4
W E
4
I/O
22
I/O
21
I/O
20
66
2M
8
512K x
x 8
512K x 8
CS
1
A
0-18
2M
8
512K x
x 8
512K x 8
2M
8
512K x
x 8
2M
512K
x 8
512K x 8
512K x 8
8
8
8
8
CS
2
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
NOTE: CS
1
& CS
2
are used as bank select
July 2002 Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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