MCIMX6L8DVN10ACR datasheet, PDF

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MCIMX6L8DVN10ACR: DescriptionI.MX 6SL ROM PERF ENHAN; Categorysemiconductor The embedded processor and controller; File Size811KB，106 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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I.MX 6SL ROM PERF ENHAN

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NXP Semiconductors

Data Sheet: Technical Data

Document Number: IMX6SLCEC

Rev. 5, 10/2017

MCIMX6LxDVN10xx

MCIMX6LxEVN10xx

i.MX 6SoloLite

Applications Processors

for Consumer Products

Package Information

Plastic Package

13 x 13 mm, 0.5 mm pitch

Ordering Information

See

Table 1 on page 3

Introduction

The i.MX 6SoloLite processor represents the latest

achievement in integrated multimedia applications

processors, which are part of a growing family of

multimedia-focused products that offer high

performance processing and are optimized for lowest

power consumption.

The processor features NXP’s advanced implementation

of the a single ARM

Cortex

-A9 MPCore™ multicore

processor, which operates at speeds up to 1 GHz. It

includes 2D graphics processor and integrated power

management. The processor provides a 32-bit

DDR3-800 memory interface and a number of other

interfaces for connecting peripherals, such as WLAN,

Bluetooth™, GPS, hard drive, displays, and camera

sensors.

The i.MX 6SoloLite processor is specifically useful for

applications, such as:

• Color and monochrome eReaders

• Entry level tablets

• Barcode scanners

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Updated Signal Naming Convention . . . . . . . . . . . . 7

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 15

3.2 Recommended Connections for Unused Analog

Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 17

4.2 Power Supplies Requirements and Restrictions . . 26

4.3 Integrated LDO Voltage Regulator Parameters . . . 27

4.4 PLL’s Electrical Characteristics . . . . . . . . . . . . . . . 29

4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 30

4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 31

4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 35

4.8 Output Buffer Impedance Parameters . . . . . . . . . . 38

4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 40

4.10 External Peripheral Interface Parameters . . . . . . . 52

Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . 80

5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . . 80

5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . . 81

Package Information and Contact Assignments . . . . . . . 82

6.1 Updated Signal Naming Convention . . . . . . . . . . . 82

6.2 13 x 13mm Package Information. . . . . . . . . . . . . . 83

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Introduction

The i.MX 6SoloLite processor features:

• Applications processor—The processor enhances the capabilities of high-tier portable applications

by fulfilling the ever increasing MIPS requirements of operating systems and games. The Dynamic

Voltage and Frequency Scaling (DVFS) provides significant power reduction, allowing the device

to run at lower voltage and frequency with sufficient MIPS for tasks, such as audio decode.

• Multilevel memory system—The multilevel memory system of each processor is based on the L1

instruction and data caches, L2 cache, and internal and external memory. The processor supports

many types of external memory devices, including DDR3, LPDDR2, NOR Flash, PSRAM,

cellular RAM, and managed NAND, including eMMC up to rev 4.4/4.41.

• Smart speed technology—The processor has power management throughout the IC that enables the

rich suite of multimedia features and peripherals to consume minimum power in both active and

various low power modes. Smart speed technology enables the designer to deliver a feature-rich

product, requiring levels of power far lower than industry expectations.

• Dynamic voltage and frequency scaling—The processor improves the power efficiency of devices

by scaling the voltage and frequency to optimize performance.

• Multimedia powerhouse—The multimedia performance of each processor is enhanced by a

multilevel cache system, NEON™ MPE (Media Processor Engine) co-processor, and a

programmable smart DMA (SDMA) controller.

• Powerful graphics acceleration—Each processor provides three independent, integrated graphics

processing units: 2D BLit engine, a 2D graphics accelerator, and dedicated OpenVG™ 1.1

accelerator.

• Interface flexibility—The processor supports connections to a variety of interfaces: LCD

controller, CMOS sensor interface (parallel), high-speed USB on-the-go with PHY, high-speed

USB host PHY, multiple expansion card ports (high-speed MMC/SDIO host and other),

10/100 Mbps Ethernet controller, and a variety of other popular interfaces (such as UART, I

C, and

S serial audio).

• Electronic Paper Display Controller—The processor integrates EPD controller that supports E Ink

color and monochrome with up to 2048 x 1536 resolution at 106 Hz refresh, 4096 x 4096 resolution

at 20 Hz refresh and 5-bit grayscale (32-levels per color channel).

• Advanced security—The processor delivers hardware-enabled security features that enable secure

e-commerce, digital rights management (DRM), information encryption, secure boot, and secure

software downloads. The security features are discussed in detail in the i.MX 6SoloLite security

reference manual (IMX6SLSRM). Contact your local NXP representative for more information.

• Integrated power management—The processor integrates linear regulators and generate internally

all the voltage levels for different domains. This significantly simplifies system power

management structure.

• GPIO with interrupt capabilities—The new GPIO pad design supports configurable dual voltage

rails at 1.8 V and 3.3 V supplies. The pad is configurable to interface at either voltage level.

1.1

Ordering Information

Table 1

provides examples of orderable part numbers covered by this data sheet.

Table 1

does not include

all possible orderable part numbers. The latest part numbers are available on

nxp.com/imx6series.

If your

i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017

NXP Semiconductors

MCIMX6L8DVN10ACR Related Products

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Description	I.MX 6SL ROM PERF ENHAN	I.MX 6SL ROM PERF ENHAN	I.MX 6SL ROM PERF ENHAN	I.MX6 SL ROM ENHANCE	I.MX 6SL ROM PERF ENHAN	I.MX 6SL ROM PERF ENHAN	I.MX 6SL ROM PERF ENHAN
Is it Rohs certified?	-	-	conform to	conform to	conform to	conform to	conform to
Maker	-	-	NXP	NXP	NXP	NXP	NXP
package instruction	-	-	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,
Reach Compliance Code	-	-	compliant	compliant	compliant	compliant	compliant
JESD-30 code	-	-	S-PBGA-B	S-PBGA-B	S-PBGA-B	S-PBGA-B	S-PBGA-B
length	-	-	13 mm	13 mm	13 mm	13 mm	13 mm
Humidity sensitivity level	-	-	3	3	3	3	3
Maximum operating temperature	-	-	95 °C	95 °C	105 °C	95 °C	105 °C
Package body material	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	-	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
Package shape	-	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	-	-	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	-	-	260	260	260	260	260
Maximum seat height	-	-	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm
Maximum supply voltage	-	-	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
Minimum supply voltage	-	-	1.375 V	1.375 V	1.375 V	1.375 V	1.375 V
surface mount	-	-	YES	YES	YES	YES	YES
technology	-	-	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	-	-	OTHER	OTHER	INDUSTRIAL	OTHER	INDUSTRIAL
Terminal form	-	-	BALL	BALL	BALL	BALL	BALL
Terminal pitch	-	-	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	-	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	-	-	40	40	40	40	40
width	-	-	13 mm	13 mm	13 mm	13 mm	13 mm
uPs/uCs/peripheral integrated circuit type	-	-	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC

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