SIT3808AC-22-33NY-12.285543X datasheet, PDF

SiT3808

1 MHz to 80 MHz High Performance MEMS VCXO

The Smart Timing Choice

Features



Applications



Any frequency between 1 MHz and 80 MHz with 6 decimal places of

accuracy

100% pin-to-pin drop-in replacement to quartz-based VCXO

Frequency stability as tight as ±10 ppm

Widest pull range options from ±25 ppm to ±1600 ppm

Industrial or extended commercial temperature range

Superior pull range linearity of ≤1%, 10 times better than quartz

LVCMOS/LVTTL compatible output

Four industry-standard packages: 2.5 mm x 2.0 mm (4-pin),

3.2 mm x 2.5mm (4-pin), 5.0 mm x 3.2 mm (6-pin), 7.0 mm x 5.0 mm

(6-pin)

Instant samples with

Time Machine II

and

field programmable

oscillators

RoHS and REACH compliant, Pb-free, Halogen-free and

Antimony-free

Telecom clock synchronization, instrumentation

Low bandwidth analog PLL, jitter cleaner, clock recovery, audio

Video, 3G/HD-SDI, FPGA, broadband and networking



Electrical Specifications

Parameter

Output Frequency Range

Frequency Stability

Table 1. Electrical Characteristics

[1, 2, 3]

Symbol

f

F_stab

Min.

1

-10

-25

-50

Aging

Operating Temperature Range

F_aging

T_use

-5

-20

-40

Supply Voltage

Vdd

1.71

2.25

2.52

2.97

Current Consumption

Standby Current

Idd

I_std

–

Pull Range

[5, 6]

Upper Control Voltage

PR

VC_U

Typ.

–

1.8

2.5

2.8

3.3

31

29

–

Max.

80

+10

+25

+50

+5

+70

+85

1.89

2.75

3.08

3.63

33

31

70

10

Unit

MHz

ppm

°C

V

mA

A

ppm

V

kΩ

pF

%

–

kHz

Contact SiTime for 16 kHz and other high bandwidth options

No load condition, f = 20 MHz, Vdd = 2.5V, 2.8V or 3.3V

No load condition, f = 20 MHz, Vdd = 1.8V

Vdd = 2.5V, 2.8V, 3.3V, ST = GND, output is Weakly Pulled Down

Vdd = 1.8V, ST = GND, output is Weakly Pulled Down

See the Absolute Pull Range and APR table on

page 10

Vdd = 1.8V, Voltage at which maximum deviation is guaranteed.

Vdd = 2.5V, Voltage at which maximum deviation is guaranteed.

Vdd = 2.8V, Voltage at which maximum deviation is guaranteed.

Vdd = 3.3V, Voltage at which maximum deviation is guaranteed.

Voltage at which minimum deviation is guaranteed.

10 years, 25°C

Extended Commercial

Industrial

Additional supply voltages between 2.5V and 3.3V can be

supported. Contact

SiTime

for additional information.

Inclusive of Initial tolerance

[4]

at 25 °C, and variation over

temperature, rated supply voltage and load.

Condition

Frequency Range

Frequency Stability and Aging

Supply Voltage and Current Consumption

VCXO Characteristics

±25, ±50, ±100, ±150, ±200,

±400, ±800, ±1600

1.7

2.4

2.7

3.2

Lower Control Voltage

Control Voltage Input Impedance

Control Voltage Input Capacitance

Linearity

Frequency Change Polarity

Control Voltage Bandwidth (-3dB)

VC_L

Z_in

C_in

Lin

–

V_BW

–

100

–

5

0.1

Positive slope

8

–

0.1

–

1

SiTime Corporation

Rev. 1.01

990 Almanor Avenue, Sunnyvale, CA 94085

(408) 328-4400

www.sitime.com

Revised January 8, 2015

SiT3808

1 MHz to 80 MHz High Performance MEMS VCXO

The Smart Timing Choice

Table 1. Electrical Characteristics

[1, 2, 3]

Parameter

Duty Cycle

Rise/Fall Time

Output High Voltage

Symbol

DC

Tr, Tf

VOH

Electrical Specifications

(continued)

Min.

45

–

90%

Typ.

–

1.5

–

Max.

55

2

–

Unit

%

ns

Vdd

Condition

All Vdds. Refer to

Note 11

for definition of Duty Cycle

Vdd = 1.8V, 2.5v, 2.8V or 3.3V, 10% - 90% Vdd level

IOH = -7 mA (Vdd = 3.0V or 3.3V)

IOH = -4 mA (Vdd = 2.8V or 2.5V)

IOH = -2 mA (Vdd = 1.8V)

IOL = 7 mA (Vdd = 3.0V or 3.3V)

IOL = 4 mA (Vdd = 2.8V or 2.5V)

IOL = 2 mA (Vdd = 1.8V)

For the OE/ST pin for 6-pin devices

See Figure 7 for startup resume timing diagram

f = 40 MHz, all Vdds. For other freq, T_oe = 100 ns + 3 clock

periods

See Figure 8 for resume timing diagram

f = 20 MHz, Vdd = 2.5V, 2.8V or 3.3V

f = 20 MHz, Vdd = 1.8V

f = 20 MHz, Integration bandwidth = 12 kHz to 20 MHz, All Vdds

LVCMOS Output Characteristics

Output Low Voltage

VOL

–

10%

Vdd

Input Characteristics

Input Pull-up Impedance

Input Capacitance

Startup Time

OE Enable/Disable Time

Resume Time

RMS Period Jitter

RMS Phase Jitter (random)

Z_in

C_in

T_start

T_oe

T_resume

T_jitt

T_phj

–

100

5

–

7

1.5

2

0.5

250

–

10

180

10

Jitter

2

3

1

ps

kΩ

pF

ms

ns

ms

Startup and Resume Timing

Notes:

1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.

2. The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and at

25°C temperature.

3. All max and min specifications are guaranteed across rated voltage variations and operating temperature ranges, unless specified otherwise

4. Initial tolerance is measured at Vin = Vdd/2

5. Absolute Pull Range (APR) is defined as the guaranteed pull range over temperature and voltage.

6. APR = pull range (PR) - frequency stability (F_stab) - Aging (F_aging)

Rev. 1.01

Page 2 of 11

www.sitime.com

SiT3808

1 MHz to 80 MHz High Performance MEMS VCXO

The Smart Timing Choice

Table 2. Pin Description. 4-Pin Configuration

(For 2.5 x 2.0 mm and 3.2 x 2.5 mm packages)

1

2

3

4

Symbol

VIN

GND

CLK

VDD

Input

Power

Output

Power

Electrical ground

Oscillator output

Power supply voltage

[7]

GND

2

3

Top View

Functionality

VIN

1

4

0-Vdd: produces voltage dependent frequency change

VDD

CLK

Note:

7. A capacitor value of 0.1 µF between VDD and GND is recommended.

Figure 1.

Table 3. Pin Description. 6-Pin Configuration

(For 5.0 x 3.2 mm and 7.0 x 5.0 mm packages)

1

Symbol

VIN

Input

No

Connect

2

NC/OE/ ST

Output

Enable

Standby

3

4

5

6

GND

CLK

NC

VDD

Power

Output

No

Connect

Power

Functionality

0-Vdd: produces voltage dependent frequency change

H or L or Open: No effect on output frequency or other device

functions

H or Open

[8]

: specified frequency output

L: output is high

H or Open

[8]

: specified frequency output

L: output is low (weak pull down)

[9]

. Oscillation stops

Electrical ground

Oscillator output

H or L or Open: No effect on output frequency or other device

functions

Power supply voltage

[10]

VIN

NC/OE/ST

GND

1

6

Top View

VDD

NC

CLK

2

5

3

4

Figure 2.

Notes:

8. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 2 in the 6-pin package is not externally driven. If pin 2 needs to be left floating, use

the NC option

9. Typical value of the weak pull-down impedance is 5 mΩ

10. A capacitor value of 0.1 µF between VDD and GND is recommended.

Table 4. Absolute Maximum Limits

Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of

the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.

Parameter

Storage Temperature

VDD

Electrostatic Discharge

Soldering Temperature (follow standard Pb free soldering guidelines)

Min.

-65

-0.5

–

Max.

150

4

2000

260

Unit

°C

V

°C

Table 5. Thermal Consideration

Parameter

7050

5032

3225

2520



JA, 4 Layer Board

(°C/W)

191

97

109

117



JA, 2 Layer Board

(°C/W)

263

199

212

222



JC, Bottom

(°C/W)

30

24

27

26

Table 6. Environmental Compliance

Parameter

Mechanical Shock

Mechanical Vibration

Temperature Cycle

Solderability

Moisture Sensitivity Level

Condition/Test Method

MIL-STD-883F, Method 2002

MIL-STD-883F, Method 2007

JESD22, Method A104

MIL-STD-883F, Method 2003

MSL1 @ 260°C

Rev. 1.01

Page 3 of 11

www.sitime.com

SiT3808

1 MHz to 80 MHz High Performance MEMS VCXO

The Smart Timing Choice

Phase Noise Plot

-100

-110

-120

-130

-140

-150

-160

-170

3

10

Integrated random phase jitter (RMS, 12kHz-5MHz): 0.52ps

Phase Noise (dBc/Hz)

10

4

10

Frequency Offset (Hz)

5

10

6

Figure 3. Phase Noise, 10 MHz, 3.3V, LVCMOS Output

Test Circuit and Waveform

Vdd

Vout

Test

Point

6

15pF

(including probe

and fixture

capacitance)

Power

Supply

0.1µF

5

Vout

Test

Point

4

Power

Supply

0.1µF

3

4

15pF

(including probe

and fixture

capacitance)

1

2

1

2

3

OE/ST Function

Vc

OE/ST Function

Vc

Vdd

Figure 4. Test Circuit (4-Pin Device)

Figure 5. Test Circuit (6-Pin Device)

tr

90% Vdd

50%

10% Vdd

High Pulse

(TH)

Period

tf

Low Pulse

(TL)

Figure 6. Waveform

Note:

11. Duty Cycle is computed as Duty Cycle = TH/Period.

12. SiT3808 supports the configurable duty cycle feature. For custom duty cycle at any given frequency, contact

SiTime.

Rev. 1.01

Page 4 of 11

www.sitime.com

SiT3808

1 MHz to 80 MHz High Performance MEMS VCXO

The Smart Timing Choice

Timing Diagram

Vdd

50% Vdd

Pin 4 Voltage

T_start

No Glitch

during start up

80% Vdd, 2.5/2.8/3.3V devices

80% Vdd, 1.8V devices

Vdd

ST Voltage

T_resume

CLK Output

T_start: Time to start from power-off

T_resume: Time to resume from ST

Figure 7. Startup Timing (OE/ST Mode)

u

Vdd

50% Vdd

OE Voltage

T_oe

Figure 8. Standby Resume Timing (ST Mode Only)

Vdd

OE Voltage

50% Vdd

T_oe

CLK Output

HZ

T_oe: Time to re-enable the clock output

T_oe: Time to put the output in High Z mode

Figure 9. OE Enable Timing (OE Mode Only)

Figure 10. OE Disable Timing (OE Mode Only)

Notes:

13. SiT3808 supports “no runt” pulses and “no glitch” output during startup or resume.

14. SiT3808 supports gated output which is accurate within rated frequency stability from the first cycle.

Rev. 1.01

Page 5 of 11

www.sitime.com

Parameter Name	Attribute value
type	MEMS VCXO
frequency	12.285543MHz
Function	-
output	LVCMOS
Voltage - Power	3.3V
frequency stability	±25ppm
Absolute pulling range (APR)	±800ppm
Operating temperature	-20°C ~ 70°C
Current - Power (maximum)	33mA
grade	-
Installation type	surface mount
Package/casing	4-SMD, no leads
size/dimensions	0.126" long x 0.098" wide (3.20mm x 2.50mm)
Height - Installation (maximum)	0.032"（0.80mm）
Current - Power (disabled) (maximum)	-

SIT3808AC-22-33NY-12.285543X

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