XM20C64
64K
XM20C64
High Speed AUTOSTORE
™
NOVRAM
8K x 8
FEATURES
DESCRIPTION
The XM20C64 is a high speed nonvolatile RAM Module.
It is comprised of four Xicor X20C16 high speed
NOVRAMs, a high speed decoder and decoupling
capacitors mounted on a co-fired multilayered Ceramic
substrate. The XM20C64 is configured 8K x 8 and is fully
decoded. The module is a 28-lead DIP conforming to the
industry standard pinout for SRAMs.
The XM20C64 fully supports the AUTOSTORE feature,
providing hands-off automatic storing of RAM data
into E
2
PROM when V
CC
falls below the AUTOSTORE
threshold.
The XM20C64 is a highly reliable memory component,
supporting unlimited writes to RAM, a minimum 1,000,000
store cycles and a minimum 100 year data retention.
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High Speed: t
AA
= 55ns
NO Batteries!!
Low Power CMOS
AUTOSTORE
™
NOVRAM
—Automatically Stores RAM data to E
2
PROM
upon Power-fail Detection
Open Drain AUTOSTORE Output Pin
—Provides Interrupt or Status Information
—Linkable to System Reset Circuitry
Auto Recall
—Automatically Recalls E
2
PROM Data During
Power-on
Fully Decoded Module
Full Military Temperature Range
— –55
°
C to +125
°
C
High Reliability
—Endurance: 1,000,000 Nonvolatile Store Cycles
—Data Retention: 100 Years
ESD Protection
—
≥
2KV All Pins
Also Available in 66 Pin PUMA Package
FUNCTIONAL DIAGRAM
2
25
31
23
PIN CONFIGURATION
NE
A0–A10
NE
OE
WE
NE
OE
WE
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
AS
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
I/O
30
2
A11
A12
2
3
A0
A1
Y0
Y1
Y2
Y3
CE
1
4
5
6
7
2
25
31
23
25
31
23
NE
OE
WE
CE
A0–A10
I/O
30
NE
OE
WE
CE
A0–A10
I/O
30
2
25
31
23
AUTOSTORE
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
©Xicor, Inc. 1991, 1995, 1996 Patents Pending
3874-1.6 6/20/96 T0/C2/D0 NS
3874 FHD F02.1
NE
OE
WE
CE
A0–A10
A0–A10
I/O
30
I/O0–I/O7
3874 FHD F01
1
Characteristics subject to change without notice
XM20C64
PIN DESCRIPTIONS
Addresses (A
0
-A
12
)
The address inputs select an 8-bit memory location
during read and write operations.
Chip Enable (CE)
The chip enable input must be LOW to enable all read,
write and user requested nonvolatile operations.
Output Enable (OE)
During normal RAM operations
OE
controls the data
output buffers. If a hardware nonvolatile operation is
selected (NE =
CE
= LOW) and
OE
strobes LOW, a
recall operation will be initiated.
OE
LOW will always disable a STORE operation regard-
less of the state of
NE, WE,
and
CE
so long as the
internal transfer has not commenced.
Write Enable (WE)
During normal RAM operations
WE
=
CE
= LOW will
cause data to be written to the RAM address pointed to
by the A
0
-A
12
inputs.
Nonvolatile Enable (NE)
The nonvolatile input controls the transfer of data from
the E
2
PROM array to the RAM array, when strobed
LOW in conjunction with
CE
=
OE
= LOW.
Data In/Data Out (I/O
0
-I/O
7
)
Data is written to or read from the X20C64 through the
I/O pins. The I/O pins are placed in the high impedance
state when either
CE
or
OE
is HIGH or when
NE
is LOW.
AUTOSTORE Output (AS)
AS
is an open-drain output. When it is asserted (driving
LOW) it indicates V
CC
has fallen below the AUTOSTORE
threshold and an internal store operation has been
initiated. Because
AS
is an open drain output it may be
wire-ORed with multiple open drain outputs and used as
an interrupt input to a microprocessor.
DEVICE OPERATION
NOVRAM operations are identical to those of a standard
SRAM. When
OE
and
CE
are asserted data is presented
at the I/Os from the address location pointed to by the
A
0
–A
12
inputs.
RAM write operations are initiated and the address input
is latched by the HIGH to LOW transition of
CE
or
WE,
whichever occurs last. Data is latched on the rising edge
of either
CE
or
WE,
whichever occurs first.
An array recall, E
2
PROM data transferred to RAM, is
initiated whenever
OE
=
NE
=
CE
= LOW. A recall is also
performed automatically upon power-up.
Command Sequence Operations
The X20C64 employs a version of the industry standard
Software Data Protection (SDP). The end user can
select various options for transferring data from RAM
into the E
2
PROM array.
All command sequences are comprised of three specific
data/address write operations performed with
NE
LOW.
A Store operation can be directly selected by issuing a
Store command. The user may also enable and disable
the AUTOSTORE function through the software data
protection sequence. Refer to Table 1 below for a
complete description of the command sequence.
Operational Notes
The X20C64 should be viewed as a subsystem when
writing software for the various store operations. The
module contains four discrete components each need-
ing to be set to the required state individually. The two
high order address bits (A
11
and A
12
) select only one of
the four components.
2
XM20C64
TABLE 1
Step
1
2
3
Operation
Write
Write
Write
A
0
–A
10
*
555
2AA
555
Data Pattern
AA
55
Command
3874 PGM T11
TABLE 2
Command
CC[H]
CD[H]
33[H]
Function
Enable Autostore
Disable Autostore
Store Operation
3874 PGM T12.2
* It should be noted, the high order addresses should remain
stable during the operations. It should also be noted that these
commands are not global, that is only one device on the module
will be affected by each command operation.
Command Sequence Timing Limits
Limits
Symbol
t
STO
t
SP
t
SPH
Note:
Parameter
Store Time
Command Write Pulse Width
Inter Command Delay
Min.
50
55
Max.
5
Units
ms
ns
ns
3874 PGM T01.1
All Write Command Sequence timings must conform to the standard write timing requirements.
Command Sequence
tSTO
ADDRESS
555
2AAA
555
OE
tSP
CE
WE
NE
tDS
DATA IN
AA
tDH
55
CMD
3874 FHD F03.1
3
XM20C64
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. –65°C to +125°C
Storage Temperature ....................... –65°C to +125°C
Voltage on any Pin with
Respect to V
SS ............................................
–1V to +7V
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the module.
This is a stress rating only and the functional operation of
the module at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect module reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Military
Min.
–55°C
Max.
+125°C
3874 PGM T06
Supply Voltage
XM20C64
Limits
5V
±10%
3874 PGM T07
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
l
CC1
Parameter
V
CC
Active Current
Min.
Max.
100
Units
mA
Test Conditions
NE
=
WE
+ V
IH
,
CE
=
OE
= V
IL,
Address Inputs = TTL Inputs @ f = 20MHz
All I/Os = Open
All Inputs = V
IH,
All I/Os = Open
All Inputs = V
CC
–0.3V All I/Os = Open
V
IN
= V
SS
to V
CC
V
IN
= V
SS
to V
CC
,
CE
= V
IH
I
CC2
I
SB
I
LI
I
LO
V
IL(1)
V
IH(1)
V
OL
V
OLAS
V
OH
V
CC
Active Current
(AUTOSTORE)
V
CC
Standby Current
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
AUTOSTORE Output
Voltage
Output HIGH Voltage
10
1.5
10
10
0.8
V
CC
+ 0.5
0.4
0.4
mA
mA
µA
µA
V
V
V
V
V
–0.5
2
I
OL
= 5mA
I
OLAS
= 1mA
I
OH
= –4mA
3874 PGM T08.2
2.4
POWER-UP TIMING
Symbol
t
PUR
t
PUST
Parameter
Power-Up (V
CC
Min.) to RAM Operation
Power-Up (V
CC
Min.) to Store Operation
Max.
500
5
Units
µs
ms
3874 PGM T09
CAPACITANCE
T
A
= +25°C, f = 1MHz, V
CC
= 5V.
Symbol
C
I/O(2)
C
IN(2)
Test
Input/Output Capacitance
Input Capacitance
Max.
40
24
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
3874 PGM T10.1
Notes:
(1) V
IL
min. and V
IH
max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
4
XM20C64
A.C. CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
Read Cycle Limits
Limits
Symbol
t
RC
t
CE
t
AA
t
OE
t
LZ(3)
t
OLZ(3)
t
HZ(3)
t
OHZ(3)
t
OH
Parameter
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
CE
Low to Output in Low Z
OE
Low to Output in Low Z
CE
High to Output in Low Z
OE
High to Output in Low Z
Output Hold
Min.
55
55
55
30
0
0
0
0
0
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
3874 PGM T03
25
25
Read Cycle Timing Diagram
tRC
ADDRESS
tCE
CE
tOE
OE
tOLZ
tLZ
I/O
tAA
Note:
tHZ
tOH
tOHZ
3874 FHD F05
(3) t
LZ
min., t
HZ
min., t
OLZ
min., and t
OHZ
min. are periodically sampled and not 100% tested. t
HZ
max. and t
OHZ
max. are
measured from the point when
CE
or
OE
return high (whichever occurs first) to the time when the outputs are no longer driven.
MODE SELECTION
CE
H
L
L
L
L
L
L
L
WE
X
H
L
L
H
H
H
L
NE
X
H
H
L
H
L
L
L
OE
X
L
X
H
H
L
H
L
Mode
Module Not Selected
Read RAM Active
Write RAM
Issue Software Command
Output Disabled
Hardware Array Recall
No Operation
Not Allowed
I/O State
High Z
Data Output
Data Input
Data Input
High Z
High Z
High Z
High Z
Power
Standby
Active
Active
Active
Active
Active
Active
Active
3874 PGM T04.1
5
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