Dual 10-Bit TxDAC+
with 2 Interpolation Filters
AD9761
®
FEATURES
Complete 10-Bit, 40 MSPS Dual Transmit DAC
Excellent Gain and Offset Matching
Differential Nonlinearity Error: 0.5 LSB
Effective Number of Bits: 9.5
Signal-to-Noise and Distortion Ratio: 59 dB
Spurious-Free Dynamic Range: 71 dB
2 Interpolation Filters
20 MSPS/Channel Data Rate
Single Supply: 3 V to 5.5 V
Low Power Dissipation: 93 mW (3 V Supply @
40 MSPS)
On-Chip Reference
28-Lead SSOP
PRODUCT DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
DCOM
DVDD
CLOCK
ACOM
AVDD
I
DAC
IOUTA
IOUTB
REFLO
FSADJ
REFIO
COMP1
COMP2
COMP3
QOUTA
QOUTB
LATCH
I
2
SLEEP
REFERENCE
DAC DATA
INPUTS
(10 BITS)
BIAS
GENERATOR
LATCH
Q
2
Q
DAC
WRITE INPUT
SELECT INPUT
MUX
CONTROL
AD9761
The AD9761 is a complete dual-channel, high speed, 10-bit
CMOS DAC. The AD9761 has been developed specifically for
use in wide bandwidth communication applications (e.g., spread
spectrum) where digital I and Q information is being processed
during transmit operations. It integrates two 10-bit, 40 MSPS
DACs, dual 2 interpolation filters, a voltage reference, and digi-
tal input interface circuitry. The AD9761 supports a 20 MSPS
per channel input data rate that is then interpolated by 2 up to
40 MSPS before simultaneously updating each DAC.
The interleaved I and Q input data stream is presented to the
digital interface circuitry, which consists of I and Q latches as
well as some additional control logic. The data is de-interleaved
back into its original I and Q data. An on-chip state machine
ensures the proper pairing of I and Q data. The data output from
each latch is then processed by a 2 digital interpolation filter
that eases the reconstruction filter requirements. The interpo-
lated output of each filter serves as the input of their respective
10-bit DAC.
The DACs utilize a segmented current source architecture com-
bined with a proprietary switching technique to reduce glitch
energy and to maximize dynamic accuracy. Each DAC provides
differential current output, thus supporting single-ended or dif-
ferential applications. Both DACs are simultaneously updated
and provide a nominal full-scale current of 10 mA. Also, the
full-scale currents between each DAC are matched to within
0.07 dB (i.e., 0.75%), thus eliminating the need for additional
gain calibration circuitry.
The AD9761 is manufactured on an advanced low cost CMOS
process. It operates from a single supply of 3 V to 5.5 V and
consumes 200 mW of power. To make the AD9761 complete, it
also offers an internal 1.20 V temperature-compensated band gap
reference.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective companies.
PRODUCT HIGHLIGHTS
1. Dual 10-Bit, 40 MSPS DACs
A pair of high performance 40 MSPS DACs optimized for low
distortion performance provide for flexible transmission of I
and Q information.
2. 2 Digital Interpolation Filters
Dual matching FIR interpolation filters with 62.5 dB stop-
band rejection precede each DAC input, thus reducing the
DACs’ reconstruction filter requirements.
3. Low Power
Complete CMOS dual DAC function operates on a low
200 mW on a single supply from 3 V to 5.5 V. The DAC
full-scale current can be reduced for lower power opera-
tion, and a sleep mode is provided for power reduction
during idle periods.
4. On-Chip Voltage Reference
The AD9761 includes a 1.20 V temperature-compensated
band gap voltage reference.
5. Single 10-Bit Digital Input Bus
The AD9761 features a flexible digital interface that allows
each DAC to be addressed in a variety of ways including dif-
ferent update rates.
6. Small Package
The AD9761 offers the complete integrated function in a
compact 28-lead SSOP package.
7. Product Family
The AD9761 Dual Transmit DAC has a pair of Dual Receive
ADC companion products, the AD9281 (8 bits) and AD9201
(10 bits).
One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A.
.O.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9761–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
DC ACCURACY
1
Integral Nonlinearity Error (INL)
T
A
= 25°C
T
MIN
to T
MAX
Differential Nonlinearity (DNL)
T
A
= 25°C
T
MIN
to T
MAX
Monotonicity (10-Bit)
ANALOG OUTPUT
Offset Error
Offset Matching between DACs
Gain Error (without Internal Reference)
Gain Error (with Internal Reference)
Gain Matching between DACs
Full-Scale Output Current
2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current
3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift
Gain Drift (without Internal Reference)
Gain Drift (with Internal Reference)
Gain Matching Drift (between DACs)
Reference Voltage Drift
POWER SUPPLY
AVDD
Voltage Range
Analog Supply Current (I
AVDD
)
DVDD
Voltage Range
Digital Supply Current at 5 V (I
DVDD
)
4
Digital Supply Current at 3 V (I
DVDD
)
4
Nominal Power Dissipation
5
AVDD and DVDD at 3 V
AVDD and DVDD at 5 V
Power Supply Rejection Ratio (PSRR)–AVDD
Power Supply Rejection Ratio (PSRR)–DVDD
OPERATING RANGE
(T
MIN
to T
Max
, AVDD = 5 V, DVDD = 5 V, I
OUTFS
= 10 mA, unless otherwise noted.)
Min
10
Typ
Max
Unit
Bits
–1.75
–2.75
±0.5
±0.7
+1.75
+2.75
LSB
LSB
LSB
LSB
–1
±0.4
+1.25
–1
±0.5
+1.75
Guaranteed over Rated Specification Temperature Range
–0.05
–0.10
–5.5
–5.5
–1.0
–1.0
±0.025
±0.05
±1.0
±1.0
±0.25
10
100
5
1.20
100
+0.05
+0.10
+5.5
+5.5
+1.0
+1.25
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
mA
V
k
pF
V
nA
V
M
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
1.14
1.26
0.1
1
0
±50
±140
±25
±50
1.25
3.0
2.7
5.0
26
5.0
15
5
93
200
5.5
29
5.5
18
V
mA
V
mA
mA
mW
mW
% of FSR/V
% of FSR/V
°C
–0.25
–0.02
–40
250
+0.25
+0.02
+85
NOTES
1
Measured at IOUTA and QOUTA, driving a virtual ground.
2
Nominal full-scale current, I
OUTFS
, is 16 the I
REF
current.
3
Use an external amplifier to drive any external load.
4
Measured at f
CLOCK
= 40 MSPS and f
OUT
= 1 MHz.
5
Measured as unbuffered voltage output into 50
R
LOAD
at IOUTA, IOUTB, QOUTA, and QOUTB; f
CLOCK
= 40 MSPS and f
OUT
= 8 MHz.
Specifications subject to change without notice.
–2–
REV. C
AD9761
DYNAMIC SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate
Output Settling Time (t
ST
to 0.025%)
Output Propagation Delay (t
PD
)
Glitch Impulse
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
AC LINEARITY TO NYQUIST
Signal-to-Noise and Distortion (SINAD)
f
OUT
= 1 MHz; CLOCK = 40 MSPS
Effective Number of Bits (ENOBs)
Total Harmonic Distortion (THD)
f
OUT
= 1 MHz; CLOCK = 40 MSPS
T
A
= 25°C
T
MIN
to T
MAX
Spurious-Free Dynamic Range (SFDR)
f
OUT
= 1 MHz; CLOCK = 40 MSPS; 10 MHz Span
Channel Isolation
f
OUT
= 8 MHz; CLOCK = 40 MSPS; 10 MHz Span
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 5 V, DVDD = 5 V, I
OUTFS
= 10 mA, Differential Transformer Coupled Output,
50
Doubly Terminated, unless otherwise noted.)
Min
40
Typ
Max
Unit
MSPS
ns
Input Clock Cycles
pV-s
ns
ns
35
55
5
2.5
2.5
56
9.0
59
9.5
–68
–67
–58
–53
dB
Bits
dB
dB
dB
dBc
59
68
90
DIGITAL SPECIFICATIONS
Parameter
(T
MIN
to T
MAX
, AVDD = 5 V, DVDD = 5 V, I
OUTFS
= 10 mA unless otherwise noted.)
Min
3.5
2.4
–10
–10
Typ
5
3
0
0
5
3
2
5
5
Max
Unit
V
V
V
V
µA
µA
pF
ns
ns
ns
ns
ns
DIGITAL INPUTS
Logic 1 Voltage @ DVDD = 5 V
Logic 1 Voltage @ DVDD = 3 V
Logic 0 Voltage @ DVDD = 5 V
Logic 0 Voltage @ DVDD = 3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (t
S
)
Input Hold Time (t
H
)
CLOCK High
CLOCK Low
Invalid CLOCK/WRITE Window (t
CINV
)*
Specifications subject to change without notice.
t
S
DB9–DB0
DAC
INPUTS
1.3
0.9
+10
+10
1
5
*t
CINV
is an invalid window of 4 ns duration beginning 1 ns
after
the rising edge of WRITE in which the rising edge of CLOCK
must not
occur.
t
H
I DATA
Q DATA
SELECT
WRITE
NOTE: WRITE AND CLOCK CAN BE
TIED TOGETHER. FOR TYPICAL EXAMPLES,
REFER TO DIGITAL INPUTS AND INTERLEAVED
INTERFACE CONSIDERATION SECTION.
CLOCK
t
CINV
Figure 1. Timing Diagram
REV. C
–3–
AD9761
DIGITAL FILTER SPECIFICATIONS
Parameter
MAXIMUM INPUT CLOCK RATE (f
CLOCK
)
DIGITAL FILTER CHARACTERISTICS
Pass Bandwidth
1
: 0.005 dB
Pass Bandwidth: 0.01 dB
Pass Bandwidth: 0.1 dB
Pass Bandwidth: –3 dB
Linear Phase (FIR Implementation)
Stop-Band Rejection: 0.3 f
CLOCK
to 0.7 f
CLOCK
Group Delay
2
Impulse Response Duration
3
–40 dB
–60 dB
(T
MIN
to T
MAX
, AVDD = 2.7 V to 5.5 V, DVDD = 2.7 V to 5.5 V, I
OUTFS
= 10 mA, unless
otherwise noted.)
Min
40
0.2010
0.2025
0.2105
0.239
–62.5
32
28
40
Typ
Max
Unit
MSPS
f
OUT
/f
CLOCK
f
OUT
/f
CLOCK
f
OUT
/f
CLOCK
f
OUT
/f
CLOCK
dB
Input Clock Cycles
Input Clock Cycles
Input Clock Cycles
NOTES
1
Excludes SINx/x characteristic of DAC.
2
Defined as the number of data clock cycles between impulse input and peak of output response.
3
55 input clock periods from input to I DAC, 56 to Q DAC. Propagation delay is delay from data input to DAC update.
Specifications subject to change without notice.
0
–20
Table I. Integer Filter Coefficients for 43-Tap Half-Band
FIR Filter
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
Upper Coefficient
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(37)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
H(28)
H(27)
H(26)
H(25)
H(24)
H(23)
Integer Value
1
0
–3
0
8
0
–16
0
29
0
–50
0
81
0
–131
0
216
0
–400
0
1264
1998
OUTPUT (dBFS)
–40
–60
–80
–100
–120
0
0.1
0.2
0.3
0.4
FREQUENCY RESPONSE (DC to f
CLOCK
/2)
0.5
Figure 2a. FIR Filter Frequency Response
1
0.9
0.8
0.7
NORMALIZED OUTPUT
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
0
5
10
15
20
25
TIME (Samples)
30
35
40
Figure 2b. FIR Filter Impulse Response
–4–
REV. C
AD9761
ORDERING GUIDE
Model
Package
Description
Package
Option
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead SSOP
q
JA
= 109°C/W
AD9761ARS
28-Lead Shrink Small Outline (SSOP) RS-28
AD9761ARSRL 28-Lead Shrink Small Outline (SSOP) RS-28
AD9761-EB
Evaluation Board
ABSOLUTE MAXIMUM RATINGS*
Parameter
AVDD
DVDD
ACOM
AVDD
CLOCK, WRITE
SELECT, SLEEP
Digital Inputs
IOUTA, IOUTB
QOUTA, QOUTB
COMP1, COMP2
COMP3
REFIO, FSADJ
REFLO
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
With
Respect to
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
DCOM
ACOM
ACOM
ACOM
ACOM
ACOM
ACOM
Min
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–0.3
–1.0
–1.0
–0.3
–0.3
–0.3
–0.3
–65
Max
+6.5
+6.5
+0.3
+6.5
DVDD + 0.3
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
+0.3
150
+150
300
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
*Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
2.7V TO
5.5V
3V TO
5.5V
0.1F
DVDD DCOM
COMP2
LATCH
I
AVDD
0.1F
AVSS COMP1
I
DAC
0.1F
MINI-CIRCUITS
T1-1T
100
TO HP3589A
SPECTRUM/NETWORK
ANALYZER
50 INPUT
50
20pF
COMP3
IOUTA
IOUTB
REFLO
2x
TEKTRONIX
AWG-2021
DIGITAL
DATA
DB9–DB0
AD9761
REFIO
FSADJ
QOUTA
QOUTB
50
0.1F
R
SET
2k
20pF
MINI-CIRCUITS
T1-1T
100
TO HP3589A
SPECTRUM/NETWORK
ANALYZER
50 INPUT
50
20pF
CLOCK
OUT MARKER 1
SELECT
WRITE
RETIMED
CLOCK
OUTPUT*
CLOCK
LATCH
Q
MUX
CONTROL
2x
Q
DAC
50
SLEEP
20pF
LE CROY 9210
PULSE GENERATOR
*AWG2021
CLOCK RETIMED SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK.
Figure 3. Basic AC Characterization Test Setup
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD9761 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. C
–5–
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