INTEGRATED CIRCUITS
74F827
10-bit buffer/line driver, non-inverting
(3-State)
Product data
Replaces Product specification 74F827/74F828 of 1994 Dec 5
2004 Jan 21
Philips
Semiconductors
Philips Semiconductors
Product data
10-bit buffer/line driver, non-inverting (3-State)
74F827
FEATURES
•
High impedance NPN base inputs for reduced loading (20
µA
in
HIGH and LOW states)
DESCRIPTION
The 74F827 10-Bit buffer provides high performance bus interface
buffering for wide data/address paths or buses carrying parity. The
device has NOR Output Enables (OE0, OE1) for maximum control
flexibility.
TYPICAL
PROPAGATION DELAY
6.0ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
60 mA
•
I
IL
is 20
µA
vs FAST family spec of 600
µA
•
Ideal where high speed, light bus loading and increased fan-in are
required
•
Controlled rise and fall times to minimize ground bounce
•
Glitch free power-up in 3-State
•
Flow through pinout architecture for microprocessor oriented
applications
TYPE
74F827
•
Outputs sink 64 mA
•
74F827 is available in SSOP type II package
ORDERING INFORMATION
COMMERCIAL RANGE: V
CC
= 5 V
±
10%; T
amb
= 0
°
C to +70
°
C
Type number
Package
Name
N74F827N
N74F827D
N74F827DB
DIP24
SO24
SSOP24
Description
plastic dual in-line package; 24 leads (300 mil)
plastic small outline package; 24 leads; body width 7.5 mm
plastic shrink small outline package; 24 leads; body width 5.3 mm
Version
SOT222-1
SOT137-1
SOT340-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0-D9
OE0-OE1
Q0-Q9
Data inputs
Output enable inputs (active-LOW)
Data outputs
DESCRIPTION
74F(U.L.)
HIGH/LOW
1.0/0.033
1.0/0.033
1200/106.7
LOAD VALUE
HIGH / LOW
20
µA
/ 20
µA
20
µA
/ 20
µA
24 mA / 64 mA
NOTES:
One (1.0) FAST Unit Load is defined as: 20
µA
in the HIGH state and 0.6 mA in the LOW state.
PIN CONFIGURATION
OE0
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 OE1
D8 10
D9 11
GND 12
SF00266
2004 Jan 21
2
Philips Semiconductors
Product data
10-bit buffer/line driver, non-inverting (3-State)
74F827
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
1
13
&
EN1
2
3
4
5
6
7
8
9
10 11
2
1
23
22
21
20
19
18
17
16
15
14
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
1
13
OE0
OE1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
3
4
5
6
7
23 22 21 20 19 18 17 16 15 14
8
9
10
V
CC
= Pin 24
GND = Pin 12
11
SF00267
SF00268
LOGIC DIAGRAM
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D8
10
D9
11
1
OE0
OE1
13
23
Q0
V
CC
= Pin 24
GND = Pin 12
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
SF00272
FUNCTION TABLE
INPUTS
OEn
L
L
H
H
L
X
Z
=
=
=
=
Dn
L
H
X
OUTPUTS
OPERATING MODE
Qn
L
H
Z
Transparent
Transparent
High impedance
HIGH voltage level
LOW voltage level
Don’t care
High impedance “off” state
2004 Jan 21
3
Philips Semiconductors
Product data
10-bit buffer/line driver, non-inverting (3-State)
74F827
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in HIGH output state
Current applied to output in LOW output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to +V
CC
128
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
HIGH-level input voltage
LOW-level input voltage
Input clamp current
HIGH-level output current
LOW-level output current
Operating free-air temperature range
PARAMETER
Min
4.5
2.0
–
–
–
–
0
Nom
5.0
–
–
–
–
–
–
Max
5.5
–
0.8
–18
–24
64
+70
V
V
V
mA
mA
mA
°C
UNIT
2004 Jan 21
4
Philips Semiconductors
Product data
10-bit buffer/line driver, non-inverting (3-State)
74F827
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
1
V
CC
= MIN,
V
IL
= MAX
MAX,
V
IH
= MIN
V
CC
= MIN,
V
IL
= MAX
MAX,
V
IH
= MIN
V
CC
= MIN,
V
IL
= MAX
MAX,
V
IH
= MIN
±
10% V
CC
I
O
= –15 mA
15
OH
±
5% V
CC
±
10% V
CC
I
O
= –24 mA
24
OH
±
5% V
CC
±
10% V
CC
I
O
= 64 mA
OL
±
5% V
CC
LIMITS
MIN
2.4
2.4
2.0
2.0
–
–
–
–
–
–
–
–
–100
–
V
CC
= MAX
–
–
TYP
2
–
3.3
–
–
–
0.42
–0.73
–
–
–
–
–
–
50
70
60
MAX
–
–
–
–
0.55
0.55
–1.2
100
20
–20
50
–50
–225
70
100
90
UNIT
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
mA
mA
mA
mA
V
O
OH
HIGH level output voltage
HIGH-level
V
O
OL
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CC
LOW-level
LOW level output voltage
Input clamp voltage
Input current at maximum input voltage
HIGH-level input current
LOW-level input current
Off-state output current,
HIGH voltage applied
Off-state output current,
LOW voltage applied
Short circuit output current
3
I
CCH
Supply current (total)
I
CCL
I
CCZ
V
CC
= MIN; I
I
= I
IK
V
CC
= 0 V; V
I
= 7.0 V
V
CC
= MAX; V
I
= 2.7 V
V
CC
= MAX; V
I
= 0.5 V
V
CC
= MAX; V
O
= 2.7 V
V
CC
= MAX; V
O
= 0.5 V
V
CC
= MAX
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under operating conditions for the applicable type.
2. All typical values are at V
CC
= 5 V, T
amb
= 25
°C.
3. Not more than one output should be shorted at one time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a HIGH output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests.
In any sequence of parameter tests, I
OS
tests should be performed last.
2004 Jan 21
5