EEWORLDEEWORLDEEWORLD

Part Number

Search

EPF10K50EQC240-3

Description
IC FPGA 189 I/O 240QFP
CategoryProgrammable logic devices    Programmable logic   
File Size2MB,182 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Download Datasheet Parametric View All

EPF10K50EQC240-3 Online Shopping

Suppliers Part Number Price MOQ In stock  
EPF10K50EQC240-3 - - View Buy Now

EPF10K50EQC240-3 Overview

IC FPGA 189 I/O 240QFP

EPF10K50EQC240-3 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIntel
package instructionFQFP, QFP240,1.3SQ,20
Reach Compliance Codecompliant
ECCN code3A991
Other features2880 LOGIC ELEMENTS
maximum clock frequency140 MHz
JESD-30 codeS-PQFP-G240
JESD-609 codee0
length32 mm
Humidity sensitivity level3
Number of I/O lines189
Number of entries189
Number of logical units2880
Output times189
Number of terminals240
Maximum operating temperature70 °C
Minimum operating temperature
organize189 I/O
Output functionMIXED
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Encapsulate equivalent codeQFP240,1.3SQ,20
Package shapeSQUARE
Package formFLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)220
power supply2.5,2.5/3.3 V
Programmable logic typeLOADABLE PLD
propagation delay0.8 ns
Certification statusNot Qualified
Maximum seat height4.1 mm
Maximum supply voltage2.7 V
Minimum supply voltage2.3 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width32 mm
Package Information Datasheet for
Mature Altera Devices
DS-PKG-16.8
This datasheet provides package and thermal resistance information for mature
Altera
®
devices. Package information includes the ordering code reference, package
acronym, leadframe material, lead finish (plating), JEDEC outline reference, lead
coplanarity, weight, moisture sensitivity level, and other special information. The
thermal resistance information includes device pin count, package name, and
resistance values.
This datasheet includes the following sections:
“Device and Package Cross Reference” on page 1
“Thermal Resistance” on page 23
“Package Outlines” on page 44
f
For more package and thermal resistance information about Altera devices that are
not listed in this datasheet, refer to the
Package and Thermal Resistance
page of the
Altera website.
For information about trays, tubes, and dry packs, refer to
AN 71: Guidelines for
Handling J-Lead, QFP, and BGA Devices.
RoHS-compliant devices are compatible with leaded-reflow temperatures. For more
information, refer to
Altera’s RoHS-Compliant Devices
literature page.
f
f
Device and Package Cross Reference
Table 2
through
Table 22
lists the device, package type, and number of pins for each
Altera device listed in this datasheet. Altera devices listed in this datasheet are
available in the following packages:
Ball-Grid Array (BGA)
Ceramic Pin-Grid Array (PGA)
FineLine BGA (FBGA)
Hybrid FineLine BGA (HBGA)
Plastic Dual In-Line Package (PDIP)
Plastic Enhanced Quad Flat Pack (EQFP)
Plastic J-Lead Chip Carrier (PLCC)
Plastic Quad Flat Pack (PQFP)
Power Quad Flat Pack (RQFP)
Thin Quad Flat Pack (TQFP)
Ultra FineLine BGA (UBGA)
© December 2011
Altera Corporation
Package Information Datasheet for Mature Altera Devices

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号