EPM3512AQC208-7 datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> EPM3512AQC208-7

EPM3512AQC208-7: DescriptionIC CPLD 512MC 7.5NS 208QFP; CategoryProgrammable logic devices Programmable logic; File Size2MB，182 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

Download Datasheet Parametric View All

EPM3512AQC208-7 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	EPM3512AQC208-7	-	-	View	Buy Now

EPM3512AQC208-7 Overview

IC CPLD 512MC 7.5NS 208QFP

EPM3512AQC208-7 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	FQFP, QFP208,1.2SQ,20
Reach Compliance Code	compliant
ECCN code	3A991
Is Samacsys	N
Other features	YES
In-system programmable	YES
JESD-30 code	S-PQFP-G208
JESD-609 code	e0
JTAG BST	YES
length	28 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	172
Number of macro cells	512
Number of terminals	208
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 172 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP208,1.2SQ,20
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	220
power supply	2.5/3.3,3.3 V
Programmable logic type	EE PLD
propagation delay	7.5 ns
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	28 mm
Base Number Matches	1

Preview

Download Datasheet

View All

Package Information Datasheet for

Mature Altera Devices

DS-PKG-16.8

This datasheet provides package and thermal resistance information for mature

Altera

devices. Package information includes the ordering code reference, package

acronym, leadframe material, lead finish (plating), JEDEC outline reference, lead

coplanarity, weight, moisture sensitivity level, and other special information. The

thermal resistance information includes device pin count, package name, and

resistance values.

This datasheet includes the following sections:

■

“Device and Package Cross Reference” on page 1

“Thermal Resistance” on page 23

“Package Outlines” on page 44

For more package and thermal resistance information about Altera devices that are

not listed in this datasheet, refer to the

Package and Thermal Resistance

page of the

Altera website.

For information about trays, tubes, and dry packs, refer to

AN 71: Guidelines for

Handling J-Lead, QFP, and BGA Devices.

RoHS-compliant devices are compatible with leaded-reflow temperatures. For more

information, refer to

Altera’s RoHS-Compliant Devices

literature page.

Device and Package Cross Reference

Table 2

through

Table 22

lists the device, package type, and number of pins for each

Altera device listed in this datasheet. Altera devices listed in this datasheet are

available in the following packages:

■

Ball-Grid Array (BGA)

Ceramic Pin-Grid Array (PGA)

FineLine BGA (FBGA)

Hybrid FineLine BGA (HBGA)

Plastic Dual In-Line Package (PDIP)

Plastic Enhanced Quad Flat Pack (EQFP)

Plastic J-Lead Chip Carrier (PLCC)

Plastic Quad Flat Pack (PQFP)

Power Quad Flat Pack (RQFP)

Thin Quad Flat Pack (TQFP)

Ultra FineLine BGA (UBGA)

Altera Corporation

Package Information Datasheet for Mature Altera Devices

Recommended Resources

Single power supply and low power consumption instrument amplification circuit diagram with stable performance

RC filter circuita

Automatic exhaust fan circuit

dog barking trainer

Electronic parrot circuit

Sawtooth wave oscillator composed of integrating circuit and comparator

TI Fuel Gauge Application Guide: As lithium batteries are increasingly used, people are paying more and more attention to and demanding more about the safety of lithium batteries and the user experience of battery life, and the deman...; qwqwqw2088 TI Technology Forum

Broadcom Wi-Fi 6E technology makes the Galaxy S21 Ultra shine: Samsung recently released three new smartphones, one of which is the Galaxy S21 Ultra, the first phone based on Wi-Fi 6E. Broadcom provides the BCM4389 chip for the device.Samsung's new Galaxy lineup ...; okhxyyo RF/Wirelessly

Simulation Problems with Strobe Display: I imitated the examples in Teacher Xia Yuwen's bookThe code is as follows: `timescale 1 ns/ 1 ps module LAMP_vlg_tst(); // constants// general purpose registers reg eachvec; // test vector input regis...; chenbingjy EE_FPGA Learning Park

dsp28335 phase shift full bridge easy to understand program: This program is in the ADC.h function Do data processing in the interrupt void adc_isr(void) function: /* * ADC.c * * Created on: 2017年8月5日 *Author: chris */#include "DSP2833x_Device.h"// DSP2833x Hea...; 灞波儿奔 DSP and ARM Processors

Optimizing DSP Power Budget by Adjusting Voltage Regulators: System-level power conservation and power budget optimization are key to many applications. For example, data center operators strive to control energy consumption, portable device designers seek to r...; Aguilera Microcontroller MCU

[Erha Image Recognition Artificial Intelligence Vision Sensor] Review 3: Firmware Upgrade via HUSKYLENS Uploader: The HuskyLens AI camera uses the new generation AI chip Kendryte K210, which has a built-in 64-bit 400MHz dual-core RISC-V processor and runs neural network algorithms more than 1,000 times faster tha...; mameng Domestic Chip Exchange

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components