AMIS-30422
Micro-Stepping Stepper
Motor Bridge Controller
Introduction
The AMIS−30422 is a micro-stepping stepper motor bridge
controller for large current range bipolar applications. The chip
interfaces via a SPI interface with an external controller in order to
control two external power NMOS H−bridges. It has an on-chip
voltage regulator, current sensing, self adapting PWM controller and
pre-driver with smart slope control switching allowing the part to be
EMC compliant with industrial and automotive applications. It uses a
proprietary PWM algorithm for reliable current control.
The AMIS−30422 contains a current translation table and takes the
next micro-step depending on the clock signal on the “NXT” input pin
and the status of the “DIR” (direction) register or input pin. The chip
provides a so-called “Speed and Load Angle” output. This allows the
creation of stall detection algorithms and control loops based on load
angle to adjust torque and speed.
The AMIS−30422 is implemented in a mature technology, enabling
fast high voltage analog circuitry and multiple digital functionalities
on the same chip. The chip is fully compatible with automotive
voltage requirements.
The AMIS−30422 is easy to use and ideally suited for large current
stepper motor applications in the automotive, industrial, medical and
marine environment. With the on−chip voltage regulator it further
reduces the BOM for mechatronic stepper applications.
Key Features
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1 48
QFN48
CASE 485AJ
MARKING DIAGRAM
1
AMIS30422
0C422−001
AWLYYWW
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Dual H−Bridge Pre−Drivers for 2−Phase Stepper Motors
Programmable Current via SPI
On−chip Current Translator
SPI Interface
Speed and Load Angle Output
9 Step Modes from Full Step up to 128 Micro−Steps
Current−Sense via Two External Sense Resistors
PWM Current Control with Automatic Selection of Fast and Slow
Decay
Low EMC PWM with Selectable Voltage Slopes
Full Output Protection and Diagnosis
Thermal Warning and Shutdown
Compatible with 3.3 V Microcontrollers
Integrated 3.3 V Regulator to Supply External Microcontroller
Integrated Reset Function to Reset External Microcontroller
Integrated Watchdog Function
These Devices are Pb−Free and are RoHS Compliant
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 44 of this data sheet.
©
Semiconductor Components Industries, LLC, 2013
March, 2013
−
Rev. 0
1
Publication Order Number:
AMIS−30422/D
AMIS−30422
BLOCK DIAGRAM
VREGH
VDD
CPN
CPP
VCP
VBB
OSC
Chargepump
MOTXP
MOTXN
CLK
CS
DI
DO
POR
EMC
P
W
M
I−sense
TRANSLATOR
GXTL
GXTR
OTP
GXBL
GXBR
RSENSXP
RSENSXN
+
−
COMP
NXT
DIR
Logic &
Registers
Load
Angle
Temp.
Sense
CLR
SLA
WD
ERR
HOLDCUR
EMC
P
W
M
I−sense
GYTL
GYTR
Band−
gap
GYBL
GYBR
RSENSYP
RSENSYN
MOTYP
MOTYN
+
−
COMP
AMIS−30422
TEST
GND
REF
GND
CPN
VBB
NC
Figure 1. Block Diagram AMIS−30422
GXBL
PIN OUT
GND
VCP
CPP
NC
NC
NC
38
NC
37
36
35
34
33
32
44
43
42
41
40
47
46
NC
MOTXP
GXTL
GXBR
MOTXN
GXTR
RSENSXP
RSENSXN
REF
NC
VDD
GND
1
2
3
4
5
6
7
8
9
10
11
12
17
18
19
20
21
22
14
15
16
23
24
13
45
39
48
GYBL
MOTYP
GYTL
GYBR
MOTYN
GYTR
RSENSYP
RSENSYN
NC
DIR
NXT
TEST
AMIS−30422
31
30
29
28
27
26
25
HOLDCUR
VREGH
ERR
CLR
SLA
WD
NC
NC
CLK
CS
DI
Figure 2. Pin Out AMIS−30422
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2
DO
AMIS−30422
Table 1. PIN LIST AND DESCRIPTION
Name
MOTXP
GXTL
GXBR
MOTXN
GXTR
RSENSXP
RSENSXN
REF
VDD
GND
VREGH
SLA
ERRb
CLR
WDb
HOLDCUR
CLK
CSb
DI
DO
TEST
NXT
DIR
RSENSYN
RSENSYP
GYTR
MOTYN
GYBR
GYTL
MOTYP
GYBL
GND
VBB
CPN
CPP
VCP
GND
GXBL
Pin
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
40
41
42
43
44
45
48
1, 10, 19,
20, 28,
37, 38,
39, 46,
47
Positive end of phase X−coil
Gate of external NMOS FET of the X bridge top left side
Gate of external NMOS FET of the X bridge bottom right side
Negative end of phase X−coil
Gate of external NMOS FET of the X bridge top right side
Resistor sense of the X bridge positive pin
Resistor sense of the X bridge negative pin
Maximum Coil Current Setting
Low voltage supply output (needs external decoupling capacitor)
Ground, heat sink
High voltage supply output
Speed and Load Angle output
Error output
Clear input
Watchdog and Power On Reset output
Hold Current Input
SPI Clock input
SPI Chip Select input
SPI Data input
SPI Data output
Test input. To be tied to ground.
Next Microstep input
Direction input
Resistor sense of the Y bridge negative pin
Resistor sense of the Y bridge positive pin
Gate of external NMOS FET of the Y bridge top right side
Negative end of phase Y−coil
Gate of external NMOS FET of the Y bridge bottom right side
Gate of external NMOS FET of the Y bridge top left side
Positive end of phase Y−coil
Gate of external NMOS FET of the Y bridge bottom left side
Ground, heat sink
High voltage supply input
Negative connection of charge pump capacitor
Positive connection of charge pump capacitor
Charge Pump filter capacitor
Ground, heat sink
Gate of external NMOS FET of the X bridge bottom left side
Description
Type
Analog I/O
Analog Output
Analog Output
Analog I/O
Analog Output
Analog Input
Analog Input
Analog Input
Supply
Supply
Analog output
Analog output
Digital Output
Digital Input
Digital Output
Digital Input
Digital Input
Digital Input
Digital Input
Digital Output
Digital Input
Digital Input
Digital Input
Analog Input
Analog Input
Analog Output
Analog I/O
Analog Output
Analog Output
Analog I/O
Analog Output
Supply
Supply
Analog I/O
Analog I/O
Analog I/O
Supply
Analog Output
Type 9
Type 1
Type 3
Type 1
Type 4
Type 1
Type 1
Type 1
Type 6
Type 2 or 4
Type 5
Type 2 or 4
Type 7
Type 8
Equivalent
Schematic
NC
Not connected or connect with ground
NOTE:
Output type of WDb− and ERRb−pin is selectable through SPI.
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3
AMIS−30422
EQUIVALENT SCHEMATICS
Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified
representations of the circuits used.
VDD
VDD
IN
R
pd
OUT
TYPE 1: CLK, DI, NXT, DIR, TEST Input
TYPE 2: WDb, ERRb Open Drain Output
VDD
VDD
R
pu
IN
OUT
TYPE 3: CSb Input
VDD
TYPE 4: DO, WDb, ERRb Push Pull Output
VDD
IN
R
out
SLA
TYPE 5:
VDD
VDD
TYPE 6: SLA Analog Output
VBB1
2V
IN
R
REF
VDD
VBB
TYPE 7:
NOTE:
TYPE 8: VDD Power Supply
TYPE 9: VBB Power Supply
Output type of WDb− and ERRb−pin is selectable through SPI, DO−pin is push−pull output with tristate
Figure 3. In− and Output Equivalent Diagrams
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4
AMIS−30422
ELECTRICAL SPECIFICATION
Table 2. ABSOLUTE MAXIMUM RATINGS
(Notes 1 and 2)
Symbol
V
BB
I
load
V
RSENS
V
LVIO
I
SLA
T
ST
T
J
V
HBM
V
HBM
V
MM
V
CDM
Analog DC supply voltage (Note 3)
Logic supply external load current, Normal Mode
Logic supply external load current, Sleep Mode
Voltage on pins RSENSXP, RSENSXN, RSENSYP and RSENYN
Voltage on digital I/O pins, REF−pin and SLA−pin
Parameter
Min
−0.3
0
0
−2.0
−0.3
Max
+40
−10
−1
+2.0
3.6
V
DD
+ 0.3
Load current on SLA−pin
Storage temperature
Junction Temperature under bias (Note 4)
Human Body Model electrostatic discharge immunity (Note 5)
Human Body Model electrostatic discharge immunity, high voltage pins (Note 6)
Machine Model electrostatic discharge immunity (Note 7)
Charge Device Model electrostatic discharge immunity (Note 8)
0
−55
−50
−2
−4
−150
−500
−40
+160
+175
+2
+4
+150
+500
mA
°C
°C
kV
kV
V
V
Unit
V
mA
mA
V
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. If more than one value is mentioned, the most stringent applies.
2. Convention: currents flowing in the circuit are defined as positive.
3. +36 V < V
BB
< +40 V limited to 1 day over lifetime
4. Circuit functionality not guaranteed.
5. According to JESD−A114
6. High Voltage Pins MOTxx, VBB, GND; According to JESD−A114
7. According to JESD−A114
8. According to STM5.3.1−1999
RECOMMEND OPERATION CONDITIONS
Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the
functionality of the chip outside these operating ranges is not guaranteed. Operating outside the recommended operating ranges
for extended periods of time may affect device reliability.
Table 3. OPERATING RANGES
Symbol
V
BB
V
DD
T
J
Analog DC supply
Logic Supply Output Voltage (Normal Mode)
Junction temperature (Note 9)
Parameter
Min
+6
+3.0
−40
Max
+30
+3.6
+125
Unit
V
V
°C
9. High junction temperature can result in reduced lifetime.
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