Features
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Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store
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Configuration Programs for Field Programmable Gate Arrays (FPGAs)
3.3V Output Capability
5V Tolerant I/O Pins
Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT40K and AT94K Devices, Altera FLEX
®
, APEX
™
Devices,
Lucent ORCA
®
FPGAs, Xilinx XC3000
™
, XC4000
™
, XC5200
™
, Spartan
®
, Virtex
®
FPGAs,
Motorola MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Low-power CMOS FLASH Process
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System
Reconfiguration
Fast Serial Download Speeds up to 33 MHz
Endurance: 5,000 Write Cycles Typical
FPGA
Configuration
Flash Memory
AT17F040
AT17F080
Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators)
provide an easy-to-use, cost-effective configuration memory for Field Programmable
Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC,
44-lead PLCC and 44-lead TQFP, see Table 1. The AT17F Series Configurator uses a
simple serial-access procedure to configure one or more FPGA devices.
The AT17F Series Configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1.
AT17F Series Packages
Package
8-lead LAP
20-lead PLCC
44-lead PLCC
44-lead TQFP
AT17F040
Yes
Yes
–
–
AT17F080
Yes
Yes
Yes
Yes
Rev. 3039G–CNFG–4/2004
1
Pin Configuration
8-lead LAP
DATA
CLK
RESET/OE
CE
1
2
3
4
8
7
6
5
VCC
SER_EN
CEO (A2)
GND
20-lead PLCC
3
2
1
20
19
NC
GND
PAGESEL0
NC
NC
9
10
11
12
13
NC
DATA
NC
VCC
NC
CLK
NC
RESET/OE
PAGESEL1
CE
4
5
6
7
8
18
17
16
15
14
NC
SER_EN
PAGE_EN
READY
CEO (A2)
20-lead PLCC (Virtex
®
Pinout)
(1)(2)
3
2
1
20
19
NC
CE
GND
NC
CEO (A2)
9
10
11
12
13
CLK
NC
DATA
VCC
NC
NC
NC
NC
NC
RESET/OE
4
5
6
7
8
18
17
16
15
14
SER_EN
NC
NC
READY
NC
Notes:
1. 20-lead PLCC (Virtex
®
pinout) is only available in the AT17F040.
2. Virtex pinout is compatible with the XC17V and XC18V Series PROM.
2
AT17F040/080
3039G–CNFG–4/2004
3039G–CNFG–4/2004
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
10
11
44 PLCC
44 TQFP
NC
RESET/OE
PAGESEL0
CE
NC
NC
GND
PAGESEL1
NC
CEO(A2)
NC
44
43
42
41
40
39
38
37
36
35
34
NC
CLK
NC
NC
DATA
PAGE_EN
VCC
NC
NC
SER_EN
NC
NC
RESET/OE
PAGESEL0
CE
NC
NC
GND
PAGESEL1
NC
CEO/A2
NC
18
19
20
21
22
23
24
25
26
27
28
12
13
14
15
16
17
18
19
20
21
22
6
5
4
3
2
1
44
43
42
41
40
NC
CLK
NC
NC
DATA
PAGE_EN
VCC
NC
NC
SER_EN
NC
39
38
37
36
35
34
33
32
31
30
29
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
AT17F040/080
3
Block Diagram
READY
Power-on
Reset
Reset
Clock/Oscillator
Logic
CLK
PAGE_EN
PAGESEL0
PAGESEL1
Config. Page
Select
CEO(A2)
Serial Download Logic
2-wire Serial Programming
DATA
Flash
Memory
CE/WE/OE
Data
Address
CE
Control Logic
RESET/OE
SER_EN
Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK)
interface directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration device without
requiring an external intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and
enable the address counter. When RESET/OE is driven Low, the configuration device
resets its address counter and tri-states its DATA pin. The CE pin also controls the out-
put of the AT17F Series Configurator. If CE is held High after the RESET/OE reset
pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subse-
quently driven High, the counter and the DATA output pin are enabled. When
RESET/OE is driven Low again, the address counter is reset and the DATA output pin is
tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
4
AT17F040/080
3039G–CNFG–4/2004
AT17F040/080
Pin Description
AT17F040
Name
DATA
CLK
PAGE_EN
PAGESEL0
PAGESEL1
RESET/OE
CE
GND
CEO
A2
READY
SER_EN
V
CC
I/O
I/O
I
I
I
I
I
I
–
O
6
I
O
I
–
–
7
8
15
17
20
15
18
20
–
7
8
15
17
20
29
41
44
23
35
38
14
13
6
14
27
21
8
LAP
1
2
–
–
–
3
4
5
20
PLCC
2
4
16
11
7
6
8
10
20 PLCC
(Virtex)
1
3
–
–
–
8
10
11
8
LAP
1
2
–
–
–
3
4
5
AT17F080
20
PLCC
2
4
16
11
7
6
8
10
44
PLCC
2
5
1
20
25
19
21
24
44
TQFP
40
43
39
14
19
13
15
18
DATA
(1)
CLK
(1)
PAGE_EN
(2)
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
Input used to enable page download mode. When PAGE_EN is high the configuration
download address space is partitioned into 4 equal pages. This gives users the ability to
easily store and retrieve multiple configuration bitstreams from a single configuration
device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be
remain low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no
effect.
Notes:
1. This pin has an internal 20 KΩ pull-up resistor.
2. This pin has an internal 30 KΩ pull-down resistor.
5
3039G–CNFG–4/2004
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