28LV64A
64K (8K x 8) Low Voltage CMOS EEPROM
FEATURES
• 2.7V to 3.6V Supply
• Read Access Time—300 ns
• CMOS Technology for Low Power Dissipation
- 8 mA Active
- 50
µ
A CMOS Standby Current
• Byte Write Time—3 ms
• Data Retention >200 years
• High Endurance - Minimum 100,000 Erase/Write
Cycles
• Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data Polling
• Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
- V
CC
Detector
- Pulse Filter
- Write Inhibit
• Electronic Signature for Device Identification
• Organized 8Kx8 JEDEC Standard Pinout
- 28-pin Dual-In-Line Package
- 32-pin Chip Carrier (Leadless or Plastic)
- 28-pin Thin Small Outline Package (TSOP)
8x20mm
- 28-pin Very Small Outline Package (VSOP)
8x13.4mm
• Available for Extended Temperature Ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
PACKAGE TYPES
RDY/BSY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
NC
A8
A6
5
A9
A5
6
A11 A4
7
A3
8
OE
A10 A2
9
A1
10
CE
A0
11
I/O7
NC
12
I/O6
I/O0
13
I/O5
I/O4
I/O3
2
RDY/BSY
1
NU
4
A7
3
A12
32
Vcc
31
WE
18
19
30
NC
29
A8
28
A9
27
A11
26
NC
25
OE
24
A10
23
CE
22
I/O7
21
I/O6
14
15
16
17
• Pin 1 indicator on PLCC on top of package
OE
A11
A9
A8
NC
WE
Vcc
RDY/BSY
A12
A7
A6
A5
A4
A3
OE
A11
A9
A8
NC
WE
V
CC
RDY/BSY
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
22
23
24
25
26
27
28
1
2
3
4
5
6
7
DESCRIPTION
The Microchip Technology Inc. 28LV64A is a CMOS 64K non-vol-
atile electrically Erasable PROM organized as 8K words by 8 bits.
The 28LV64A is accessed like a static RAM for the read or write
cycles without the need of external components. During a “byte
write”, the address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Fol-
lowing the initiation of write cycle, the device will go to a busy state
and automatically clear and write the latched data using an inter-
nal control timer. To determine when the write cycle is complete,
the user has a choice of monitoring the Ready/Busy output or
using Data polling. The Ready/Busy pin is an open drain output,
which allows easy configuration in ‘wired-or’ systems. Alterna-
tively, Data polling allows the user to read the location last written
to when the write operation is complete. CMOS design and pro-
cessing enables this part to be used in systems where reduced
power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in applica-
tions.
BLOCK DIAGRAM
I/O0...................I/O7
VSS
VCC
CE
OE
WE
Rdy/
Busy
A0
I
I
I
I
I
I
I
I
I
I
I
A12
Data Protection
Circuitry
Chip Enable/
Output Enable
Control Logic
Auto Erase/Write
Timing
Program Voltage
Generation
Y
Decoder
Data
Poll
Input/Output
Buffers
L
a
t
c
h
e
s
X
Decoder
©
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
I/O1
I/O2
Vss
NU
I/O3
I/O4
I/O5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Y Gating
64K bit
Cell Matrix
DS21113B-page 1
20
DIP/SOIC
PLCC/LCC
A10
CE
I/07
I/06
I/05
I/04
I/03
Vss
I/02
I/01
I/00
A0
A1
A2
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
V
SS
I/O2
I/O1
I/O0
A0
A1
A2
TSOP
VSOP
28LV64A
1.0
ELECTRICAL
CHARACTERISTICS
TABLE 1-1:
Name
A0 - A12
CE
OE
WE
I/O0 - I/O7
RDY/Busy
V
CC
V
SS
NC
NU
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
Ready/Busy
+ Power Supply
Ground
No Connect; No Internal Connection
Not Used; No External Connection is
Allowed
PIN FUCTION TABLE
Function
Address Inputs
MAXIMUM RATINGS*
VCC and input voltages w.r.t. V
SS
...... -0.6V to + 6.25V
Voltage on OE w.r.t. V
SS
...................... -0.6V to +13.5V
Voltage on A9 w.r.t. V
SS
....................... -0.6V to +13.5V
Output Voltage w.r.t. V
SS
............... -0.6V to VCC+0.6V
Storage temperature .......................... -65˚C to +150˚C
Ambient temp. with power applied .....-55
°
C to +125
°
C
*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is
not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
TABLE 1-2:
READ/WRITE OPERATION DC CHARACTERISTICS
V
CC
= 2.7 to 3.6V
Commercial (C): Tamb =
0
°
C to 70
°
C
Industrial
(I): Tamb = -40
°
C to 85
°
C
Parameter
Input Voltages
Input Leakage
Input Capacitance
Output Voltages
Status
Logic “1”
Logic “2”
—
—
Logic “1”
Logic “0”
—
—
TTL input
Symbol
V
IH
V
IL
I
LI
C
IN
V
OH
V
OL
I
LO
C
OUT
I
CC
Min
2.0
—
—
2.0
Max
0.6
5
6
Units
V
V
µ
A
pF
V
V
µ
A
pF
mA
Conditions
0.3
—
—
—
5
12
8
Output Leakage
Output Capacitance
Power Supply Current, Activity
Power Supply Current, Standby
TTL input
I
CC
(
S
)
TTL
TTL input
I
CC
(
S
)
TTL
CMOS input I
CC
(
S
)
CMOS
—
2
3
100
mA
mA
µ
A
V
IN
= 0V to V
CC
+1
Vin = 0V; Tamb = 25
°
C;
f = 1 MHz (Note 1)
I
OH
= -100
µ
A
I
OL
= 1.0 mA
I0
L
= 2.0 mA for RDY/Busy
V
OUT
= 0V to V
CC
+0.1V
V
OUT
= 0V; Tamb = 25
°
C;
f = 1 MHz (Note 1)
f = 5 MHz (Note 2)
I
O
= OmA
V
CC
= 3.3
CE = V
IL
CE = V
IH
(0
°
C to 70
°
C
°
)
CE = V
IH
(-40
°
C to 85
°
C
°
)
CE = V
CC
-3.0 to V
CC
+1
Note 1: Not 100% tested.
2: AC power supply current above 5 MHz: 2 mA/Mhz.
DS21113B-page 2
Preliminary
©
1996 Microchip Technology Inc.
28LV64A
TABLE 1-3:
READ OPERATION AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
V
IH
= 2.0V; V
IL
= 0.6V; V
OH
= V
OL
= V
CC
/2
1 TTL Load + 100 pF
20 ns
Commercial (C): Tamb = 0
°
C to +70
°
C
Industrial
(I) : Tamb = -40
°
C to +85
°
C
Max
Units
Conditions
OE = CE = V
IL
OE = V
IL
CE = V
IL
(Note 1)
(Note 1)
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE High to Output Float
Output Hold from Address, CE or
OE, whichever occurs first.
Sym
28LV64-30
Min
t
ACC
t
CE
t
OE
t
OFF
t
OH
—
—
—
—
0
0
10M
300
300
150
60
—
—
ns
ns
ns
ns
ns
cycles
Endurance
25
°
C, Vcc = 5.0V,
Block Mode (Note 2)
Note 1: Not 100% tested.
2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1:
READ WAVEFORMS
V
IH
Address
V
IL
V
IH
CE
V
IL
t
CE(2)
Address Valid
V
IH
OE
V
IL
V
OH
Data
V
OL
t
ACC
V
IH
WE
V
IL
Notes: (1) t
OFF
is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
(3) This parameter is sampled and is not 100% tested
t
OFF(1,3)
t
OE(2)
High Z
t
OH
Valid Output
High Z
©
1996 Microchip Technology Inc.
Preliminary
DS21113B-page 3
28LV64A
TABLE 1-4:
BYTE WRITE AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:
Parameter
Address Set-Up Time
Address Hold Time
Data Set-Up Time
Data Hold Time
Write Pulse Width
OE Hold Time
OE Set-Up Time
Data Valid Time
Time to Device Busy
Write Cycle Time (28LV64A)
V
IH
= 2.0V; V
IL
= 0.6V; V
OH
= V
OL
= V
CC
/2
1 TTL Load + 100 pF
20 ns
Commercial (C): Tamb = 0°C to +70°C
Industrial
(I) : Tamb = -40°C to +85°C
Max
Units
Remarks
Sym
Min
t
AS
t
AH
t
DS
t
DH
t
WPL
t
OEH
t
OES
t
DV
t
DB
t
WC
10
100
120
10
150
10
10
1000
50
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
1.5 ms typical
(Note 2)
(Note 1)
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the
positive edge of CE or WE, whichever occurs first.
2:
Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until t
DH
after the positive edge of WE or CE, whichever occurs first.
FIGURE 1-2:
PROGRAMMING WAVEFORMS
Address
V
IH
V
IL
V
IH
V
IL
t
AS
t
DV
t
AH
t
WPL
t
DS
t
DH
CE, WE
Data In
V
IH
V
IL
t
OES
OE
V
IH
V
IL
t
OEH
V
OH
Rdy/Busy
Busy
V
OL
twc
t
DB
Ready
DS21113B-page 4
Preliminary
©
1996 Microchip Technology Inc.
28LV64A
FIGURE 1-3:
V
IH
Address
V
IL
Address Valid
t
ACC
t
CE
t
WPH
DATA POLLING WAVEFORMS
Last Written
Address Valid
V
IH
CE
V
IL
V
IH
WE
V
IL
t
WPL
t
OE
V
IH
OE
V
IL
t
DV
V
IH
Data
V
IL
Data In
Valid
t
WC
I/O7 Out
True Data Out
FIGURE 1-4:
CHIP CLEAR WAVEFORMS
V
IH
CE
V
IL
V
H
OE
V
IH
V
IH
WE
V
IL
t
W
= 10ms
t
S
= t
H
= 1µs
V
H
= 12.0V ±0.5V
t
S
t
W
t
H
TABLE 1-5:
SUPPLEMENTARY CONTROL
Mode
CE
V
IL
V
IL
OE
V
H
V
IL
V
IH
WE
V
IH
A
I
X
A9 = V
H
A9 = V
H
V
CC
V
CC
V
CC
V
CC
I/O
I
Data Out
Data In
Chip Clear
Extra Row Read
Extra Row Write
Note:
V
H
= 12.0V
±
0.5V
©
1996 Microchip Technology Inc.
Preliminary
DS21113B-page 5
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