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LT1122BCN8#PBF

Description
IC OPAMP JFET 14MHZ 8DIP
CategoryAnalog mixed-signal IC    Amplifier circuit   
File Size268KB,14 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Environmental Compliance
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LT1122BCN8#PBF Overview

IC OPAMP JFET 14MHZ 8DIP

LT1122BCN8#PBF Parametric

Parameter NameAttribute value
Brand NameLinear Technology
Is it Rohs certified?conform to
MakerLinear ( ADI )
Parts packaging codeDIP
package instructionDIP, DIP8,.3
Contacts8
Manufacturer packaging codeN
Reach Compliance Codecompliant
ECCN codeEAR99
Amplifier typeOPERATIONAL AMPLIFIER
ArchitectureVOLTAGE-FEEDBACK
Maximum average bias current (IIB)0.0006 µA
Maximum bias current (IIB) at 25C0.000075 µA
Nominal Common Mode Rejection Ratio98 dB
frequency compensationYES
Maximum input offset voltage1400 µV
JESD-30 codeR-PDIP-T8
JESD-609 codee3
length9.78 mm
low-biasYES
low-dissonanceNO
Humidity sensitivity level1
Negative supply voltage upper limit-20 V
Nominal Negative Supply Voltage (Vsup)-15 V
Number of functions1
Number of terminals8
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP8,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply+-15 V
Certification statusNot Qualified
Maximum seat height4.445 mm
minimum slew rate45 V/us
Nominal slew rate70 V/us
Maximum slew rate10 mA
Supply voltage upper limit20 V
Nominal supply voltage (Vsup)15 V
surface mountNO
technologyBIPOLAR
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Nominal Uniform Gain Bandwidth14000 kHz
Minimum voltage gain95000
width7.62 mm
LT1122
Fast Settling, JFET Input
Operational Amplifier
FEATURES
n
DESCRIPTION
340ns Typ
540ns Max
60V/µs Min
14MHz
1.2 MHz
60°
600µV Max
75pA Max
600pA Max
40pA Max
150pA Max
The
LT
®
1122
JFET input operational amplifier combines
high speed and precision performance.
A unique poly-gate JFET process minimizes gate series
resistance and gate-to-drain capacitance, facilitating wide
bandwidth performance, without degrading JFET transis-
tor matching.
It slews at 80V/µs and settles in 340ns. The LT1122 is
internally compensated to be unity-gain stable, yet it has
a bandwidth of 14MHz at a supply current of only 7mA. Its
speed makes the LT1122 an ideal choice for fast settling
12-bit data conversion and acquisition systems.
The LT1122 offset voltage of 120µV, and voltage gain of
500,000 also support the 12-bit accurate applications.
The input bias current of 10pA and offset current of 4pA
combined with its speed allow the LT1122 to be used in
such applications as high speed sample and hold ampli-
fiers, peak detectors, and integrators.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and C-Load
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
n
n
n
n
n
n
100% Tested Settling Time
to 1mV at Sum Node, 10V Step
Tested with Fixed Feedback Capacitor
Slew Rate
Gain-Bandwidth Product
Power Bandwidth (20V
P-P
)
Unity-Gain Stable; Phase Margin
Input Offset Voltage
Input Bias Current
25°C
70°C
Input Offset Current
25°C
70°C
Low Distortion
APPLICATIONS
n
n
n
n
n
n
n
n
Fast 12-Bit D/A Output Amplifiers
High Speed Buffers
Fast Sample-and-Hold Amplifiers
High Speed Integrators
Voltage to Frequency Converters
Active Filters
Log Amplifiers
Peak Detectors
TYPICAL APPLICATION
12-Bit Voltage Output D/A Converter
+
Large-Scale Response
CF
2
0mA TO 2mA
OR 4mA
3
LT1122
6
+
V
OUT
0V TO 10V
12-BIT CURRENT OUTPUT D/A CONVERTER
C
F
= 5pF TO 17pF
(DEPENDING ON D/A CONVERTER USED)
5V/DIV
LT1122•TA01
200ns/DIV
A
V
= –1
1122 TA07
1122fb
For more information
www.linear.com/LT1122
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