HYS72V64601GR-7.5 datasheet, PDF

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HYS72V64601GR-7.5: DescriptionSynchronous DRAM Module, 64MX72, 5.4ns, CMOS, PDMA168; Categorystorage; File Size296KB，20 Pages; ManufacturerInfineon; Websitehttp://www.infineon.com/

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HYS72V64601GR-7.5 Overview

Synchronous DRAM Module, 64MX72, 5.4ns, CMOS, PDMA168

HYS72V64601GR-7.5 Parametric

Parameter Name	Attribute value
Maker	Infineon
package instruction	DIMM, DIMM168
Reach Compliance Code	unknown
Is Samacsys	N
Maximum access time	5.4 ns
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-PDMA-N168
memory density	4831838208 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	72
Number of terminals	168
word count	67108864 words
character code	64000000
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX72
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIMM
Encapsulate equivalent code	DIMM168
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
Maximum standby current	0.036 A
Maximum slew rate	3.96 mA
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Base Number Matches	1

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HYS 72Vxx5/6x0GR-7.5

Low Profile PC133 Registered SDRAM-Modules

3.3 V Low Profile 168-pin PC133 Registered

SDRAM Modules for 1U Server Applications

PC133 128 MByte Module

PC133 256 MByte module

PC133 512 MByte Module

PC133 1024 MByte Module

• 168-pin Registered 8 Byte Dual-In-Line

SDRAM Module for Workstation and Server

main memory applications with 1,2” inch

(30,40 mm) height

• One bank 16M

72, 32M x 72 and 64M

and two bank 128Mx72 organization

• Optimized for ECC applications with very low

input capacitances

• JEDEC standard Synchronous DRAMs

(SDRAM) with 128Mb, 256Mb and

512Mb memory density. Stacked

components for two bank modules

• Single + 3.3 V (

0.3 V) power supply

• Auto Refresh (CBR) and Self Refresh

• Serial Presence Detect with E

PROM

• Programmable CAS Latency, Burst Length,

and Wrap Sequence (Sequential &

Interleave)

• All inputs and outputs are LVTTL compatible

• Utilizes SDRAMs in TSOPII-54 packages

with on-board registers and PLL.

• Card Sizes :

RawCard “F” and “G” 133.35 mm x 30,40 with

gold contact pads

• These modules all fully compatible with the

current industry standard PC133

specifications and fully backward compatible

to PC100 applications

• Performance:

-7.5

CK3

AC3

CK2

AC2

Unit

MHz

Clock Frequency (max.) @ CL = 3

Clock Access Time (min.)@ CL = 3

Clock Frequency (max.) @ CL = 2

Clock Access Time (min.)@ CL = 2

133

5.4

100

The HYS 72Vxx5/6x0GR-7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs)

organized as 16M

72, 32M x 72, 64M

72 and 128M x 72 high speed memory arrays designed with x4 or x8

organised Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered

on-DIMM and the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces

capacitive loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling

capacitors are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a

serial E

PROM using the 2-pin I

C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the

second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible

8-byte interface in a 133.35 mm long footprint. This module family is designed with 30,40 mm (1.2 inch) maximum

height for 1U Server Applications b ased on JEDEC standard RawCards “F” and “G”.

INFINEON Technologies

1.02

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