Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74ABT573A
FEATURES
•
74ABT573A is flow-through pinout version of 74ABT373
•
Inputs and outputs on opposite side of package allow easy
•
3-State output buffers
•
Common output enable
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
•
Power-up 3-State
•
Power-up reset
DESCRIPTION
The 74ABT573A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
and 200 V per Machine Model
interface to microprocessors
The 74ABT573A device is an octal transparent latch coupled to
eight 3-State output buffers. The two sections of the device are
controlled independently by Enable (E) and Output Enable (OE)
control gates. The 74ABT573A is functionally identical to the
74ABT373 but has a flow-through pinout configuration to facilitate
PC board layout and allow easy interface with microprocessors.
The data on the D inputs are transferred to the latch outputs when
the Latch Enable (E) input is High. The latch remains transparent to
the data inputs while E is High, and stores the data that is present
one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the latch operation.
When OE is Low, the latched or transparent data appears at the
outputs. When OE is High, the outputs are in the High-impedance
”OFF” state, which means they will neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled; V
O
= 0V or V
CC
Outputs disabled; V
CC
=5.5V
TYPICAL
2.8
3.3
3
6
100
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
20-Pin Plastic DIP
20-Pin plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT573A N
74ABT573A D
74ABT573A DB
74ABT573A PW
NORTH AMERICA
74ABT573A N
74ABT573A D
74ABT573A DB
74ABT573APW DH
DWG NUMBER
SOT146-1
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN
NUMBER
1
SYMBOL
OE
D0-D7
FUNCTION
Output enable input (active-Low)
Data inputs
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 E
2, 3, 4, 5,
6, 7, 8, 9
19, 18, 17,
16, 15, 14,
13, 12
11
10
20
Q0-Q7
E
GND
V
CC
Data outputs
Enable input (active-High)
Ground (0V)
Positive supply voltage
GND 10
SA00185
1995 Sep 06
1
853–1455 15703
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74ABT573A
LOGIC SYMBOL (IEEE/IEC)
1
EN
11
C1
LOGIC SYMBOL
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
2D
1
19
18
17
16
15
14
1
11
D0
E
D1
D2 D3
D4
D5
D6
D7
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
19
13
12
18
17
16
15
14
13
12
SA00187
SA00186
FUNCTION TABLE
INPUTS
OE
L
L
L
L
L
H
H
H =
h =
L =
l =
NC=
X =
Z =
↓
=
E
H
H
↓
↓
L
L
H
Dn
L
H
l
h
X
X
Dn
INTERNAL
REGISTER
L
H
L
H
NC
NC
Dn
OUTPUTS
Q0 – Q7
L
H
L
H
NC
Z
Z
Enable and read register
Latch and read register
Hold
Disable outputs
OPERATING MODE
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
No change
Don’t care
High impedance “off” state
High-to-Low E transition
LOGIC DIAGRAM
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D
D
D
D
D
D
D
D
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
11
E
1
OE
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
SA00188
1995 Sep 06
2
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74ABT573A
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
Min
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
4.5
0
2.0
0.8
–32
64
5
+85
LIMITS
Max
5.5
V
CC
V
V
V
V
mA
mA
ns/V
°C
UNIT
1995 Sep 06
3
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74ABT573A
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
Min
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
OH
High-level output voltage
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
V
OL
V
RST
I
I
I
OFF
I
PU
/I
PD
I
OZH
I
OZL
I
CEX
I
O
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current per
input pin
2
Quiescent supply current
Low-level output voltage
Power-up output low
voltage
3
Input leakage current
Power-off leakage current
Power-up/down 3-State
output current
4
3-State output High current
3-State output Low current
Output High leakage current
Output current
1
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
CC
= 2.0V; V
O
= 0.5V; V
OE
= Don’t Care;
V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
–40
100
24
100
0.5
2.5
3.0
2.0
Typ
–0.9
2.9
3.4
2.4
0.42
0.13
±0.01
±5.0
±5.0
5.0
–5.0
5.0
0.55
0.55
±1.0
±100
±50
50
–50
50
–180
250
30
250
1.5
–40
Max
–1.2
2.5
3.0
2.0
0.55
0.55
±1.0
±100
±50
50
–50
50
–180
250
30
250
1.5
T
amb
= –40°C
to +85°C
Min
Max
–1.2
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
mA
UNIT
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. For V
CC
= 2.1V to V
CC
= 5V
"
10%, a
transition time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
Dn to Qn
Propagation delay
E to Qn
Output enable time
to High and Low level
Output disable time
from High and Low level
2
1
4
5
4
5
1.5
2.2
1.2
1.8
1.2
2.7
1.5
1.2
T
amb
= +25
o
C
V
CC
= +5.0V
Typ
2.8
3.3
2.5
3.0
3.0
3.8
2.8
2.2
Max
4.0
4.8
4.0
4.4
4.5
5.3
4.1
3.4
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V
±0.5V
Min
1.5
2.2
1.2
1.8
1.2
2.7
1.5
1.2
Max
4.5
5.3
4.5
4.7
5.2
5.7
4.5
3.8
ns
ns
ns
ns
UNIT
1995 Sep 06
4
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74ABT573A
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
Setup time, High or Low
Dn to E
Hold time, High or Low
Dn to E
E pulse width
High
3
3
1
1.0
1.0
1.0
1.0
2.0
Typ
0.3
0.2
–0.1
–0.2
0.7
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
±0.5V
Min
1.0
1.0
1.0
1.0
2.0
ns
ns
ns
UNIT
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
E
V
M
V
M
V
M
OE
V
M
t
PZH
V
M
t
PHZ
V
OH
–0.3V
0V
t
w
(H)
t
PHL
Qn
V
M
t
PLH
V
M
Qn
V
M
SA00063
SA00066
Waveform 1. Propagation Delay, Enable to Output, and Enable
Pulse Width
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Dn
V
M
t
PLH
V
M
t
PHL
OE
V
M
t
PZL
V
M
t
PLZ
Qn
V
M
V
M
Qn
V
M
V
OL
+0.3V
V
OL
SA00064
SA00332
Waveform 2. Propagation Delay for Data to Outputs
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
Dn
E
1995 Sep 06
ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ
É
ÉÉÉ
É
ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ
ÉÉÉÉÉÉÉÉ ÉÉÉ
V
M
V
M
V
M
V
M
t
s
(H)
t
h
(H)
t
s
(L)
t
h
(L)
V
M
V
M
NOTE:
The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00065
Waveform 3. Data Setup and Hold Times
5
MCU
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