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EP2SGX60EF1152C3

Description
IC FPGA 534 I/O 1152FBGA
CategoryProgrammable logic devices    Programmable logic   
File Size2MB,182 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
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EP2SGX60EF1152C3 Overview

IC FPGA 534 I/O 1152FBGA

EP2SGX60EF1152C3 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
package instructionBGA, BGA1152,34X34,40
Reach Compliance Codecompliant
ECCN code3A001.A.7.A
maximum clock frequency717 MHz
Combined latency of CLB-Max4.45 ns
JESD-30 codeS-PBGA-B1152
JESD-609 codee0
length35 mm
Humidity sensitivity level3
Configurable number of logic blocks60440
Number of entries534
Number of logical units60440
Output times534
Number of terminals1152
Maximum operating temperature85 °C
Minimum operating temperature
organize60440 CLBS
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA1152,34X34,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)220
power supply1.2,1.2/3.3,3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height3.5 mm
Maximum supply voltage1.25 V
Minimum supply voltage1.15 V
Nominal supply voltage1.2 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width35 mm
Base Number Matches1
Package Information Datasheet for
Mature Altera Devices
DS-PKG-16.8
This datasheet provides package and thermal resistance information for mature
Altera
®
devices. Package information includes the ordering code reference, package
acronym, leadframe material, lead finish (plating), JEDEC outline reference, lead
coplanarity, weight, moisture sensitivity level, and other special information. The
thermal resistance information includes device pin count, package name, and
resistance values.
This datasheet includes the following sections:
“Device and Package Cross Reference” on page 1
“Thermal Resistance” on page 23
“Package Outlines” on page 44
f
For more package and thermal resistance information about Altera devices that are
not listed in this datasheet, refer to the
Package and Thermal Resistance
page of the
Altera website.
For information about trays, tubes, and dry packs, refer to
AN 71: Guidelines for
Handling J-Lead, QFP, and BGA Devices.
RoHS-compliant devices are compatible with leaded-reflow temperatures. For more
information, refer to
Altera’s RoHS-Compliant Devices
literature page.
f
f
Device and Package Cross Reference
Table 2
through
Table 22
lists the device, package type, and number of pins for each
Altera device listed in this datasheet. Altera devices listed in this datasheet are
available in the following packages:
Ball-Grid Array (BGA)
Ceramic Pin-Grid Array (PGA)
FineLine BGA (FBGA)
Hybrid FineLine BGA (HBGA)
Plastic Dual In-Line Package (PDIP)
Plastic Enhanced Quad Flat Pack (EQFP)
Plastic J-Lead Chip Carrier (PLCC)
Plastic Quad Flat Pack (PQFP)
Power Quad Flat Pack (RQFP)
Thin Quad Flat Pack (TQFP)
Ultra FineLine BGA (UBGA)
© December 2011
Altera Corporation
Package Information Datasheet for Mature Altera Devices
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