MAX II Device Family
December 2005, ver. 1.3
Errata Sheet
Introduction
This errata sheet provides updated information on MAX
®
II devices,
addresses known device issues, and includes a workaround for those
issues. Refer to
Table 1.
Table 1. MAX II Device Family Issues
Issue
Failed power-up into user mode for
slow VCCINT rise times or VCCINT
rise profiles with dips or noise near
the power-on reset (POR) trip
voltage.
Affected Devices
EPM240 revision F and earlier
EPM240G revision G and earlier
EPM570 revision C and earlier
EPM570G revision D and earlier
EPM1270/1270ES revision G and
earlier
EPM1270G revision H and earlier
EPM2210 revision C and earlier
EPM2210G revision D and earlier
EPM2210G Devices
EPM1270G Devices
Fixed Devices
EPM240 revision H and later
EPM240G revision I and later
EPM570 revision E and later
EPM570G revision F and later
EPM1270 revision I and later
EPM1270G revision J and later
EPM2210 revision E and later
EPM2210G revision F and later
(1)
(2)
Extreme AC current activity can
cause the V
CCINT
POR brown-out
trigger voltage to rise up to 1.7-V
during
DEV_OE
de-assertion or
before in-system programming.
The user flash memory (UFM) block EPM1270 ES Devices
does not support program/write or
erase operations from the logic
array interface.
The optional Schmitt trigger inputs
may glitch for falling input signal
edge rates greater than 1 µs.
EPM1270 ES Devices
EPM1270 Production Devices
EPM1270 Production Devices
EPM1270 ES Devices
The UFM block optional oscillator
output port may exhibit a single high
or low pulse after power-up
EPM1270 ES Devices
The 144-pin thin quad flat pack
(TQFP) package (T144) may exhibit
glitches on the
TCK
Joint Test Action
Group (JTAG) input pin for falling
edge rates slower than 50 ns.
May not operate for V
CCINT
brown-
out conditions at or below 2.1 V.
Does not support Serial Vector File
(.svf) format programming.
EPM1270 ES Devices
EPM1270 ES Devices
EPM1270 Production Devices
EPM1270 Production Devices
EPM1270 Production Devices
EPM1270 Production Devices
Altera Corporation
ES-M2EPM1270-1.3
1
Preliminary
MAX II Device Family
Table 1. MAX II Device Family Issues (Continued)
Issue
Affected Devices
(3)
Fixed Devices
EPM1270 engineering sample (ES) EPM1270 ES Devices
devices are not compatible with
EPM1270 production device
Programming Object Files (.pof).
Notes to
Table 1:
(1)
(2)
(3)
See the
“MAX II Power-up Issue”section
for information on distinguishing revision codes.
Altera is offering permanent recommendations and workarounds for this issue.
This issue is a permanent programming file compatibility restriction.
MAX II Power-up
Issue
The MAX II devices may not power-up and enter user mode correctly for
either of the following conditions:
1. V
CCINT
rises slower than the times shown in
Table 2.
2. V
CCINT
rise profile exhibits any non-monotonic dips or noise within the
voltage regions shown in
Table 2.
This power-up issue is only affected by the V
CCINT
supply; V
CCIO
rise
times or profiles do not affect the MAX II device behavior for this issue.
This issue affects all MAX II devices shown in
Table 1.
The failed power-up condition results in all I/O pins remaining tri-state
with weak pull-up resistors even though V
CCINT
has been fully powered.
While in this state, the JTAG port is unresponsive for programming or
boundary scan operations. User mode operation does not begin unless
V
CCINT
power to the MAX II device is recycled.
To ensure successful power-up, Altera recommends (as shown in
Table 2)
that you provide a sufficient rise time with a monotonic V
CCINT
rise
profile that contains no dips within the voltage windows.
Table 2. Recommended V
CCINT
Rise Times and V
CCINT
Noise/Dip Free Window
Device and VCCINT Operating
Voltage
MAX II (3.3V V
CCINT
)
MAX II (2.5V V
CCINT
)
Recommended V
CCINT
Rise Time
(1)
<= 1.0 ms
<= 750 µs
Recommended POR Dip/Noise
Free Window
1.5-1.8V
1.5-1.8V
2
Preliminary
Altera Corporation
EPM2210G & EPM1270G Brown-out Voltage Issue
Table 2. Recommended V
CCINT
Rise Times and V
CCINT
Noise/Dip Free Window (Continued)
Device and VCCINT Operating
Voltage
MAX IIG
Note to
Table 2:
(1)
Rise times are measured from 10% to 90% of the stead-state operating voltage.
Recommended V
CCINT
Rise Time
(1)
<= 540 µs
Recommended POR Dip/Noise
Free Window
1.3-1.65V
The MAX II POR circuitry is enhanced in later revisions to withstand
non-monotonic, slow rise times in the revision codes that are shown in
Table 1.
The die revision is identified by the alphanumeric character (Z)
before the fab code (first two alphanumeric characters) in the data code
printed on the top side of the device.
Figure 1
shows a MAX II device's
top side date code.
Figure 1. MAX II Device Top Side
A XβZ ## ####
Die Revision
EPM2210G &
EPM1270G
Brown-out
Voltage Issue
f
The POR circuitry monitors V
CCINT
(but not V
CCIO
) voltage to detect
brown-out conditions. During normal user-mode operation, the POR
circuit resets the SRAM configuration and tri-states the device I/O pins
when V
CCINT
falls approximately to or below 1.4 V. This POR circuit
brown-out trigger voltage rises to 1.55 V on MAX IIG devices when the
optional
DEV_OE
feature/pin is de-asserted or during in-system
programming.
For more information on POR trip voltages and diagrams, see the
Hot-Socketing & Power-On Reset in MAX II Devices
chapter of the
MAX II
Handbook.
For EPM2210G and EPM1270G devices, if the AC switching current on
the device’s V
CCINT
supply (I
CCINT
) is more than the thresholds shown in
Table 3
immediately before
DEV_OE
de-asserts (tri-state all I/O pins) or
before in-system programming begins, the brown-out trigger voltage can
rise as high as 1.7 V. This value is near the minimum operating voltage
(1.71 V) of the 1.8-V EPM2210G and EPM1270G devices and can lead to
unintended device reset during user-mode operation or a failed in-
system programming attempt. I
CCINT
is a function of logic element (LE)
Altera Corporation
3
Preliminary
MAX II Device Family
utilization, clock frequency, and toggle factors. You can estimate the
I
CCINT
value by using the MAX II PowerPlay Early Power Estimator
and/or the Quartus
®
II Power Analyzer.
Table 3. EPM2210G & EPM1270G I
CCINT
Thresholds for Brown-Out Trigger
Voltage Issue with DEV_OE & In-System Programming
Device
EPM2210G
EPM1270G
Current Threshold
500
300
Units
mA
mA
For
DEV_OE
use with EPM2210G and EPM1270G devices, you should
only use this feature if you can guarantee your design’s I
CCINT
is less than
the thresholds shown in
Table 3.
When enabled by the Quartus II
software, the
DEV_OE
feature does not use global resources but instead
uses dedicated circuitry to control the output enable on all design I/O
pins. For designs that cannot guarantee I
CCINT
is less the threshold, you
can use one of the four global signals to control device-wide output
enable (OE) control. Using a global signal
OE
instead of the
DEV_OE
pin
prevents the increase in POR trip voltage. The global signal
OE
requires
that you instantiate a tri-state buffer and connect an
OE
signal to all the
I/O pins in your design and assign the
OE
pin to a global signal in the
Quartus II software.
For in-system programming with EPM2210G and EPM1270G devices,
you should only use this feature if you can guarantee I
CCINT
is less than
the threshold shown in
Table 3
for the running design immediately before
in-system programming begins. For designs that can operate with I
CCINT
greater than the threshold, you must either ensure within the system that
the AC activity of the EPM2210G or EPM1270G device is reduced before
in-system programming begins or instead use the real-time ISP feature.
The real-time ISP feature does not raise the POR brown-out trigger
voltage, thus it will not be susceptible to failed in-system programming
during high switching current conditions. Using real-time ISP means the
design continues to run during the in-system programming process.
f
For more information on the real-time ISP feature, see the
Using Real-time
ISP & ISP Clamp
chapter of the
MAX II Handbook.
The following issues and support constraints affect the MAX II EPM1270
ES devices:
■
EPM1270 ES
Device Issues
UFM block does not support program/write or erase operations
from the logic array interface
4
Preliminary
Altera Corporation
EPM1270 ES Device Issues
■
■
■
■
■
■
UFM block optional oscillator output port can exhibit a single high
or low pulse after power-up
Optional Schmitt trigger inputs may glitch for falling input signal
edge rates greater than 1 µs
144-Pin TQFP package (T144) devices may exhibit glitches on the
TCK
JTAG input pin for falling edge rates slower than 50 ns
May not operate for V
CCINT
brown-out conditions at or below 2.1 V
Do not support SVF format programming
Are not compatible with the EPM1270 production device POF
All of the device issues listed above are corrected in production
EPM1270 devices.
1
UFM Block Logic Array Interface Support
The EPM1270 ES UFM block does not support write/program and erase
operations from the logic array interface. The EPM1270 ES UFM block
does support read operations from the logic array interface. The UFM can
still be initialized or programmed through the JTAG interface using the
Quartus II software with POF, Jam™ (.jam), or Jam Byte-Code (.jbc) files.
When using the
altufm
megafunction to instantiate the UFM block, the
Quartus II software issues an error for the following cases:
■
■
For the interface protocol, choosing
None
in the MegaWizard
®
Plug-
In Manager (called the
altufm_none
megafunction) and
connecting the program or erase ports of your instantiation to signals
or pins in your design results in a compilation error.
If you choose
Parallel
or
Serial Peripheral Interface (SPI)
in the
MegaWizard
®
Plug-In Manager (called the
altufm_parallel
and
altufm_spi
megafunctions), the read/write option results in a
compilation error. The read-only option will compile successfully.
Production devices will fully support the UFM erase and
program/write operations from the logic array.
1
UFM Block Oscillator Output Port Pulse
The EPM1270 ES device's optional UFM oscillator (OSC) output port, may
pulse once (high or low) at power-up when first entering into user mode
even though the oscillator enable port (OSCENA) is de-asserted at power-
up in the design. The
OSC
output can be
ANDed
with the
OSCENA
port in
the design to ensure that this port starts clocking when expected after
power-up.
Altera Corporation
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Preliminary
MCU
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