SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
Contents
1.
General Description ......................................................................................................................................................5
1.1. Features ................................................................................................................................................................5
1.1.1.
Analog (Video) Front-end..............................................................................................................................5
1.1.2.
Multi-format Video Decoder .........................................................................................................................5
1.1.3.
Video Processing ...........................................................................................................................................5
1.4. Temperature Range ..............................................................................................................................................5
2. Product Family ..............................................................................................................................................................6
3.1. Analog Front-end ..................................................................................................................................................8
Clamp and Offset ..........................................................................................................................................8
ADC with Programmable Gain Amplifier.......................................................................................................8
3.1.5.
Line Locked PLL .............................................................................................................................................9
Video Buffer ..................................................................................................................................................9
3.2. Video Decoder ......................................................................................................................................................9
Automatic Gain Control and Offset Calibration ..........................................................................................10
3.2.3.
Antialias Filtering and Decimation ..............................................................................................................10
3.2.4.
Video Decoder ............................................................................................................................................10
3.3. Video Processing .................................................................................................................................................12
3.3.1.
Time Base Corrector ...................................................................................................................................12
3.3.2.
VBI Post Processor ......................................................................................................................................12
3.3.3.
De-interlacer and Edge Smoother...............................................................................................................12
3.3.4.
Color Processing ..........................................................................................................................................12
3.3.5.
Auto Phase Detection .................................................................................................................................13
3.3.6.
Auto Position Calibration ............................................................................................................................13
3.3.7.
Auto Gain Calibration ..................................................................................................................................13
3.4. Video Path ...........................................................................................................................................................13
3.4.1.
Video Data Conversion Logic Block .............................................................................................................13
3.4.2.
Digital Parallel Video Output Interface .......................................................................................................14
3.5. Control Logic .......................................................................................................................................................15
I C Bus .........................................................................................................................................................17
4.1. Absolute Maximum Ratings ................................................................................................................................19
4.2. Normal Operating Conditions .............................................................................................................................20
4.4. DC Specifications .................................................................................................................................................21
4.5. AC Specifications .................................................................................................................................................22
4.6. Control Signal Timing Specifications ...................................................................................................................23
5.1. I C Bus Timing Diagrams ..................................................................................................................................... 24
5.3. Digital Video Output Timing Diagrams ............................................................................................................... 25
6. Pin Diagram and Pin Description ................................................................................................................................ 26
9.1. Ordering Information .......................................................................................................................................... 41
Revision History .................................................................................................................................................................. 43
5.
Figures
Figure 1.1. Typical Application of the SiI8788 Device ........................................................................................................... 5
Figure 5.1. I C Data Valid Delay (Driving Read Cycle Data) ................................................................................................. 24
Figure 5.2. Conditions for Use of RESET_N ......................................................................................................................... 24
Figure 5.4. Video Digital Output Transition Times .............................................................................................................. 25
Figure 5.5. Clock-to-Output Delay and Duty Cycle Limits ................................................................................................... 25
Table 3.2. Typical Digital Video Output Formats ................................................................................................................15
Table 3.3. Head Flags ..........................................................................................................................................................16
Table 3.4. Info Bytes ...........................................................................................................................................................16
Table 3.9. HW Configuration Data and Code Checksum.....................................................................................................17
2
Table 3.10. Control of Transmitter I C Address with CI2CA Signal .....................................................................................18
Table 4.4. Digital I/O Specifications ....................................................................................................................................21
Table 4.5. Analog Front-end Electrical Specifications .........................................................................................................22
Table 4.6. Parallel Video Output Timing Specifications ......................................................................................................23
Table 4.7. Control Signal Timing Specifications ..................................................................................................................23
Table 6.2. Configuration and Control Pins ..........................................................................................................................28
Table 6.3. Parallel RGB Output Data Pins ...........................................................................................................................29
Table 6.5. Power and Ground Connections ........................................................................................................................30
Table 6.8. RGB/YCbCr 4:4:4 Separate Sync Data Mapping .................................................................................................31
Table 6.9. YCbCr 4:2:2 Separate Sync Data Mapping..........................................................................................................32
Table 6.10. YCbCr 4:2:2 Embedded Sync Data Mapping.....................................................................................................33
Table 6.11. YCbCr Mux 4:2:2 Separate Sync Data Mapping ...............................................................................................34
Table 6.12. YCbCr Mux 4:2:2 Embedded Sync Data Mapping ............................................................................................35
Table 6.13. 12-bit RGB and YCbCr 4:4:4 Separate Sync Data Mapping ..............................................................................36
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