3D7225
MONOLITHIC 5-TAP
FIXED DELAY LINE
(SERIES 3D7225)
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range:
0.75ns through 3500ns
Delay tolerance:
2% or 0.5ns
Temperature stability:
±2%
typical (-40C to 85C)
Vdd stability:
±1%
typical (4.75V-5.25V)
Minimum input pulse width:
30% of total delay
8-pin Gull-Wing available as drop-in
replacement for hybrid delay lines
IN
O2
O4
GND
1
2
3
4
8
7
6
5
PACKAGES
VDD
O1
O3
O5
IN
NC
NC
O2
NC
O4
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
NC
O1
NC
O3
NC
O5
3D7225Z-xx SOIC-8
3D7225M-xx DIP-8
3D7225H-xx Gull-Wing
IN
NC
NC
O2
NC
O4
NC
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
NC
NC
O1
NC
O3
NC
O5
3D7225-xx
3D7225G-xx
3D7225K-xx
3D7225S-xx SOL-16
DIP-14
Gull-Wing
Unused pins
removed
For mechanical dimensions, click
here
.
For package marking details, click
here
.
FUNCTIONAL DESCRIPTION
The 3D7225 5-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 0.75ns through 700ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D7225 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.
PIN DESCRIPTIONS
IN
O1
O2
O3
O4
O5
VDD
GND
Delay Line Input
Tap 1 Output (20%)
Tap 2 Output (40%)
Tap 3 Output (60%)
Tap 4 Output (80%)
Tap 5 Output (100%)
+5 Volts
Ground
The all-CMOS 3D7225 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and space saving surface mount
8-pin SOIC and 16-pin SOL packages.
TABLE 1: PART NUMBER SPECIFICATIONS
DASH
NUMBER
-.75
-1
-1.5
-2
-2.5
-4
-5
-10
-20
-50
-100
-200
-700
TOLERANCES
TOTAL
TAP-TAP
DELAY (ns)
DELAY (ns)
3.0
±
0.5*
0.75
±
0.4
4.0
±
0.5*
1.0
±
0.5
6.0
±
0.5*
1.5
±
0.7
8.0
±
0.5*
2.0
±
0.8
10.0
±
0.5*
2.5
±
1.0
16.0
±
0.7*
4.0
±
1.3
25.0
±
1.0
5.0
±
1.5
50.0
±
1.0
10.0
±
2.0
100.0
±
2.0
20.0
±
4.0
250.0
±
5.0
50.0
±
10
500.0
±
10
100
±
20
1000
±
20
200
±
40
3500
±
70
700
±
140
Rec’d Max
Frequency
41.7 MHz
37.0 MHz
31.2 MHz
25.0 MHz
22.2 MHz
8.33 MHz
13.3 MHz
6.67 MHz
3.33 MHz
1.33 MHz
0.67 MHz
0.33 MHz
0.10 MHz
INPUT RESTRICTIONS
Absolute Max
Rec’d Min
Frequency
Pulse Width
166.7 MHz
12.0 ns
166.7 MHz
13.5 ns
166.7 MHz
16.0 ns
166.7 MHz
20.0 ns
125.0 MHz
22.5 ns
133.3 MHz
30.0 ns
66.7 MHz
37.5 ns
33.3 MHz
75.0 ns
16.7 MHz
150 ns
6.67 MHz
375 ns
3.33 MHz
750 ns
1.67 MHz
1500 ns
0.48 MHz
5250 ns
Absolute Min
Pulse Width
3.00 ns
3.00 ns
3.00 ns
3.00 ns
4.00 ns
6.00 ns
7.50 ns
15.0 ns
30.0 ns
75.0 ns
150 ns
300 ns
1050 ns
2005
Data Delay Devices
* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns
±
1.0ns
NOTE: Any dash number between .75 and 700 not shown is also available as standard.
Doc #05002
4/15/05
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7225
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D7225 five-tap delay line architecture is
shown in Figure 1. The delay line is composed of
a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time. The
delay cells are matched and share the same
compensation signals, which minimizes tap-to-
tap delay deviations over temperature and supply
voltage variations.
To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D7225 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY DEVICES
be consulted.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input frequency
and a Minimum and an Absolute Minimum
operating pulse width have been specified.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse Width
(high or low) specification, tabulated in Table 1,
determines the smallest Pulse Width of the delay
line input signal that can be reproduced, shifted
in time at the device output, with acceptable
pulse width distortion.
The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D7225 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the part number will include a
O3
O4
O5
OPERATING FREQUENCY
The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
The Maximum Operating Frequency specification
determines the highest frequency of the delay
line input signal for which the output delay
accuracy is guaranteed.
IN
O1
O2
20%
20%
20%
20%
20%
Temp & VDD
Compensation
VDD
GND
Figure 1: 3D7225 Functional Diagram
Doc #05002
4/15/05
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
3D7225
APPLICATION NOTES (CONT’D)
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at DATA
DELAY DEVICES be consulted.
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The thermal coefficient is reduced to 250 PPM/C,
which is equivalent to a variation, over the -40C
to 85C operating range, of
±2%
from the room-
temperature delay settings and/or 1.0ns,
whichever is greater. The power supply
coefficient is reduced, over the 4.75V-5.25V
operating range, to
±1%
of the delay settings at
the nominal 5.0VDC power supply and/or 1.0ns,
whichever is greater.
It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7225 programmable delay line
utilizes novel and innovative compensation
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
I
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
V
DD
+0.3
1.0
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output
Current
Low Level Output Current
Output Rise & Fall Time
SYMBOL
I
DD
V
IH
V
IL
I
IH
I
IL
I
OH
I
OL
T
R
& T
F
MIN
2.0
0.8
1.0
1.0
-4.0
TYP
3.5
MAX
5.5
UNITS
mA
V
V
µA
µA
mA
mA
2.5
ns
NOTES
-35.0
4.0
15.0
2.0
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
*I
DD
(Dynamic) = 5 * C
LD
* V
DD
* F
where: C
LD
= Average capacitance load/tap (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
Doc #05002
4/15/05
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D7225
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
5.0V
±
0.1V
Input Pulse:
High = 3.0V
±
0.1V
Low = 0.0V
±
0.1V
Source Impedance:
50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PW
IN
= 1.25 x Total Delay
Period:
PER
IN
= 2.5 x Total Delay
OUTPUT:
R
load
:
C
load
:
Threshold:
10KΩ
±
10%
5pf
±
10%
1.5V (Rising & Falling)
Device
Under
Test
10KΩ
5pf
Digital
Scope
470Ω
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER
SYSTEM
PRINTER
PULSE
GENERATOR
OUT
TRIG
IN
DEVICE UNDER
TEST (DUT)
OUT1
OUT2
OUT3
OUT4
OUT5
REF
IN
TRIG
DIGITAL SCOPE/
TIME INTERVAL COUNTER
Figure 2: Test Setup
PER
IN
PW
IN
t
RISE
INPUT
SIGNAL
2.4V
1.5V
0.6V
t
FALL
V
IH
2.4V
1.5V
0.6V
V
IL
t
PHL
t
PLH
OUTPUT
SIGNAL
1.5V
V
OH
1.5V
V
OL
Figure 3: Timing Diagram
Doc #05002
4/15/05
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
Microchip MCU
京公网安备 11010802033920号
EEWORLD
