AM49LV4608MB10IT datasheet, PDF

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AM49LV4608MB10IT: DescriptionStacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM; File Size529KB，63 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/

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AM49LV4608MB10IT Overview

Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM

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Am49LV6408M

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number

30918

Revision

Amendment

Issue Date

November 5, 2003

A D V A N C E

I N F O R M A T I O N

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4

Flash Memory Block Diagram. . . . . . . . . . . . . . . . 5

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9

Requirements for Reading Array Data ................................... 11

Page Mode Read ................................................................ 11

Writing Commands/Command Sequences ............................ 11

Write Buffer ......................................................................... 11

Accelerated Program Operation .......................................... 11

Autoselect Functions ........................................................... 11

Automatic Sleep Mode ........................................................... 12

RESET#: Hardware Reset Pin ............................................... 12

Output Disable Mode .............................................................. 12

Table 2. Am29LV640MT Top Boot Sector Architecture ..................12

Table 3. Am29LV640MB Bottom Boot Sector Architecture .............15

Figure 9. Toggle Bit Algorithm........................................................ 36

DQ2: Toggle Bit II ................................................................... 36

Reading Toggle Bits DQ6/DQ2 ............................................... 36

DQ5: Exceeded Timing Limits ................................................ 37

DQ3: Sector Erase Timer ....................................................... 37

DQ1: Write-to-Buffer Abort ..................................................... 37

Table 12. Write Operation Status ................................................... 37

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 38

Figure 10. Maximum Negative Overshoot Waveform ................... 38

Figure 11. Maximum Positive Overshoot Waveform..................... 38

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . .

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .

Pseudo SRAM DC and

Operating Characteristics . . . . . . . . . . . . . . . . . .

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 12. Test Setup.................................................................... 41

Table 13. Test Specifications ......................................................... 41

Key to Switching Waveforms. . . . . . . . . . . . . . . . 41

Figure 13. Input Waveforms and Measurement Levels ................. 41

Sector Group Protection and Unprotection ............................. 18

Table 4. Am29LV640MT Top Boot Sector Protection .....................18

Table 5. Am29LV640MB Bottom Boot Sector Protection ................18

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42

Flash Read-Only Operations ................................................. 42

Figure 14. Read Operation Timings ............................................... 42

Figure 15. Page Read Timings ...................................................... 43

Write Protect (WP#) ................................................................ 19

Temporary Sector Group Unprotect ....................................... 19

Figure 1. Temporary Sector Group Unprotect Operation................ 19

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 20

Hardware Reset (RESET#) .................................................... 44

Figure 16. Reset Timings ............................................................... 44

SecSi (Secured Silicon) Sector Flash Memory Region .......... 21

Table 6. SecSi Sector Contents ......................................................21

Figure 3. SecSi Sector Protect Verify.............................................. 22

Erase and Program Operations .............................................. 45

Figure 17. Program Operation Timings..........................................

Figure 18. Accelerated Program Timing Diagram..........................

Figure 19. Chip/Sector Erase Operation Timings ..........................

Figure 20. Data# Polling Timings

(During Embedded Algorithms)......................................................

Figure 21. Toggle Bit Timings (During Embedded Algorithms)......

Figure 22. DQ2 vs. DQ6.................................................................

Hardware Data Protection ...................................................... 22

Low VCC Write Inhibit ......................................................... 22

Write Pulse “Glitch” Protection ............................................ 22

Logical Inhibit ...................................................................... 22

Power-Up Write Inhibit ......................................................... 22

Common Flash Memory Interface (CFI) . . . . . . . 22

Command Definitions . . . . . . . . . . . . . . . . . . . . . 25

Reading Array Data ................................................................ 25

Reset Command ..................................................................... 26

Autoselect Command Sequence ............................................ 26

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 26

Word Program Command Sequence ..................................... 26

Unlock Bypass Command Sequence .................................. 27

Write Buffer Programming ................................................... 27

Accelerated Program ........................................................... 28

Figure 4. Write Buffer Programming Operation............................... 29

Figure 5. Program Operation .......................................................... 30

Temporary Sector Unprotect .................................................. 50

Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 50

Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 51

Alternate CE# Controlled Erase and Program Operations ..... 52

Figure 25. Alternate CE# Controlled Write (Erase/Program)

Operation Timings.......................................................................... 53

Pseudo SRAM AC Characteristics . . . . . . . . . . . 54

Power Up Time ....................................................................... 54

Read Cycle ............................................................................. 54

Figure 26. Pseudo SRAM Read Cycle—Address Controlled......... 54

Figure 27. Pseudo SRAM Read Cycle........................................... 55

Write Cycle ............................................................................. 56

Figure 28. Pseudo SRAM Write Cycle—WE# Control ................... 56

Figure 29. Pseudo SRAM Write Cycle—CE1#s Control ................ 57

Program Suspend/Program Resume Command Sequence ... 30

Figure 6. Program Suspend/Program Resume............................... 31

Chip Erase Command Sequence ........................................... 31

Sector Erase Command Sequence ........................................ 31

Figure 7. Erase Operation............................................................... 32

Erase Suspend/Erase Resume Commands ........................... 32

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 34

DQ7: Data# Polling ................................................................. 34

Figure 8. Data# Polling Algorithm ................................................... 34

Flash Erase And Programming Performance . . 58

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 58

BGA Package Capacitance . . . . . . . . . . . . . . . . . 58

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 60

TLB069—69-Ball Fine-pitch Ball Grid Array (FBGA)

8 x 10 mm Package ................................................................ 60

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61

DQ6: Toggle Bit I .................................................................... 35

November 5, 2003

Am49LV6408M

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