Product Specification
PE99151
Product Description
The PE99151 is a radiation tolerant point-of-load buck
regulator delivering high efficiency at V
IN
= 5V and output
currents up to 2A continuous. This single-chip solution is
perfect for Hi-Rel applications and delivers peak
efficiency exceeding 93%. A minimal external
component count and high switching frequency enables
>10 W/in
2
standard PCB designs while high efficiency
minimizes thermal concerns. All power switching devices
are integrated on-chip.
Fabricated in Peregrine’s patented UltraCMOS
®
technology, the PE99151 offers excellent power
efficiency and intrinsic radiation tolerance.
Hi-Rel 2A DC-DC Converter
Radiation Tolerant UltraCMOS
®
Monolithic Point-of-Load Synchronous
Buck Regulator with Integrated Switches
Features
Up to 2A continuous
Output voltage range from 1.0–3.6V
Table 1. Radiation Performance
TID
SEL
SEB
SET
SEFI
SEGR
100 kRad(Si)
> 90 MeV•cm
2
/mg
> 90 MeV•cm
2
/mg
> 90 MeV•cm /mg
> 90 MeV•cm
2
/mg
> 90 MeV•cm /mg
2
2
by external select resistors
Input voltage range 4.6V – 6.0V
Current mode control, pulse-by-pulse
current limit, current sharing enabled
and (N+K) redundancy compatible
shutdown mode
SYNC function, 100 kHz–5 MHz lock
range with selectable 500 kHz /1 MHz
free running frequency
Shutdown pin, Power Good output pin
for supply sequencing
Better than 1% typical initial accuracy
(25°C)
Control inputs compatible with TTL,
LVTTL, LVCMOS (2.5V and 3.3V)
and 5V CMOS
Available in ceramic hermetic packaging
and in bare die form
SEL, SEB, SEGR, SEU, SEFI: None observed, Au/60 degrees
SET: No events exceeding 30 mV transient observed @ Au,
LET=90, 60 degrees and normal incidence
Figure 1. Typical Application Diagram
Figure 2. Package Type
32-lead ceramic quad flat package
Information contained herein is classified as EAR99 under the U.S. Export
Administration Regulations. Export, re-export or diversion contrary to U.S.
law is prohibited.
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Product Specification
PE99151
Table 2. Electrical Specifications
Case Temp (T
c
) = –55 to +125 °C, V
IN
= 4.6–6.0V, V
OUT
= 1.0–3.6V (except as noted)
Parameter
Synchronous Frequency Range,
Fsw_range
Maximum Cycle-Averaged RMS
Output Current,
Imax
Supply Current (Shutdown),
IDDSD
Supply Current (No-load, 1 MHz
async),
IDD0
High Side On Resistance,
Ron,hss
Low Side On Resistance,
Ron,lss
Test current = 100 mA
Test current = 100 mA
Output Voltage
V
IN
= 5.0V, I
OUT
= Imax/2, –55≤ T
C
≤ +125 °C, Fsw = 100 kHz–1 MHz
Reference Voltage Accuracy,
Vref*
Reference Voltage Line Regulation,
Kvi (steady state)
Reference Voltage Load Regulation,
Kvo (steady state)
V
IN
= 5.0V, I
OUT
= Imax/2, Fsw = 100 kHz–1 MHz
(100 kRad post rad, Tc = 25 °C)
4.6V ≤ V
IN
≤ 6.0V, I
OUT
= 1A, V
OUT
= 2.5V, Fsw = 1 MHz
V
IN
= 5.0V, 500 mA ≤ I
OUT
≤ 1A, V
OUT
= 2.5V, Fsw = 1 MHz
Internal Oscillator and SYNC Capture
Oscillator Frequency,
FOSC_FREQ
Internal Oscillator Duty Cycle,
FOSC_DC
SYNC Lock Capture Frequency,
Sync_lock
External Sync Duty Cycle,
SYNC_DC
Current Limiting and Current Mode Control Loop
Internal Current Limit Max,
ILIMXINT
Externally Set Max Current Limit
Accuracy,
ILIMXEXT
Max voltage across Rset,
VMAXRSET
I
out
/I
rset,
G
Iref
ICOMP cap,
CICOMP
Current compensation gain, Icomp
gain,
G
ICOMP
2.3
I
OUT
set for 50% rated current
V
OUT
= 1.0V, ISET = 3.0V, ICOMP = 0V, RSEL pin shorted to ground,
not min-on-time limited
V
OUT
= 1.0V, RSET = 130Ω, ISET = 3.0V, ICOMP = 0V, RSEL = V
IN
,
not min-on-time limited
2
2
1.3
300
3
3
1.5
378
110
3
4
4
4
1.75
450
A
A
V
A/A
pF
A/V
SYNC = GND
SYNC = Open or V
IN
320
0.71
46
40
40
60
530
1
700
1.42
54
kHz
MHz
%
kHz
%
–1.5
–1.5
–0.2
–0.25
0
0
0
0
1.5
1.5
0.2
0.25
%
%
%
%
97
113
SDb = GND, V
IN
= 5.5V
SDb = GND, V
IN
= 6.0V
Condition
Min
0.1
2
1.8
3.1
3.2
5.5
17.5
160
190
Typ
Max
5
Unit
MHz
A
mA
mA
mA
mΩ
mΩ
Note: * Parameter is tested in production at –55°C, +25°C, and +125°C, and guaranteed through characterization at –40°C and +85°C.
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Product Specification
PE99151
Table 2. Electrical Specifications (Cont.)
Case Temp (T
c
) = –55 to +125 °C, V
IN
= 4.6–6.0V, V
OUT
= 1.0–3.6V (except as noted)
PGOOD
EAINM_UP_THRESH entering PGOOD window
(% of Vref)
EAINM_LO_THRESH exiting PGOOD window
(% of Vref)
EAINM_UP (% of Vref)
EAINM_LO
V_PGOOD = 0.4V
V_PGOOD = V
IN
3.5
103
83
110
89
2
1.67
8
9
64
Error Amp
EAINM leakage
EAINP leakage
EAOUT Source Current
EAOUT Sink Current
Error Amplifier Transconductance
Error Amplifier Output Resistance
EA Input offset
1 MHz internal
Undervoltage Lockout
V
IN
Rising**
Undervoltage Lockout
Undervoltage Lockout Hysteresis
Soft Start
SS pin pull-up Resistance
Internal
SSCAP
Vref Track,
VSSCAP – Vref_ext
VSSCAP = 0.5V
DC Characteristics
SDb turn-on threshold
SYNCOb low sink current,
SYNCOb I_OL
SYNCOb high leakage current,
SYNCOb I_OH
SYNC
V
IH
V
IL
V_SYNCOb = 0.4
V_SYNCOb = V
IN
V
IH
V
IL
V
OUT
= V_SDb = 0V
V
OUT
= V_SDb = 0V (100 kRad post rad, T
C
= 25 °C)
V
OUT
= V
IN
, V_SDb = 0V
Thermal
Theta_JC
Note: **Not production tested at –55 °C.
PGOOD Threshold
118
98
%
%
%
%
mA
PGOOD Hysteresis
PGOOD low sink current,
PGOOD I_OL
PGOOD high leakage current,
PGOOD I_OH
PGOOD Deglitch Time
22.5
µA
SYNCOb
cycles
Measured at 1V input
Measured at 1V input
Measured at 1V input
Measured at 1V input
EAOUT = 1.5V, DC
–490
100
0.4
3.5
–6
–345
200
1.25
6.5
4
0.2
0.2
–220
295
2.2
9.5
6
µA
µA
µA
µA
mS
MΩ
mV
3.5
3.4
4.2
3.8
400
4.59
4.1
4.2
V
V
V
mV
V
IN
Falling
V
IN
Falling (100 kRad post rad, T
C
= 25 °C)
VSSCAP = 0V
–170
1.2
16
0
170
MΩ
pF
mV
2
1.45
3.5
8
9
2
1.25
–0.09
–4
0.09
0.7
–0.001
22.5
V
V
mA
µA
V
V
mA
mA
mA
HSS Leakage
LSS Leakage
Junction to back side paddle
4
°C/W
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Technical Data subject to restrictions contained on the cover page.
Product Specification
PE99151
Figure 3.
Package
Pin Layout (Top View)
SScap
SYNC
GND
SDb
V
IN
GND
V
IN
V
IN
Table 4. Operating Ranges
Symbol
V
IN
Parameter/Condition
Power supply voltage
Operating temperature range
(case)
Min
4.6
–55
Max
6.0
125
Unit
V
o
32
31
30
29
28
27
26
25
AGND
VREF
EAINP
EAINM
EAOUT
ISET
ICOMP
RSET
1
2
3
4
5
6
7
8
24
23
22
GND
OUT
OUT
OUT
OUT
OUT
GND
GND
T
C
C
Ground
Paddle
(backside)
21
20
19
18
17
Notes: Operation should be restricted to the limits in the Operating Ranges
table.
Vin recommended maximum slew rate is 100 V/s. Refer to application
note TDAPN9915x.
Table 5. Absolute Maximum Ratings
Symbol
V
IN
T
J
Θ
JC
T
ST
I
I
I
O
I
P
Parameter/Condition
Power supply voltage
Operating temperature range
(junction)
Theta JC
Min
–0.5
–55
Max
6.5
+145
4
Unit
V
o
9
10
11
12
13
14
15
16
C
RSEL
V
IN
PGOOD
GND
V
IN
GND
SYNCOb
GND
°C/W
o
Storage temperature range (case)
DC into any signal input
DC into any signal output
DC into any
single
power pin
–65
–10
–50
–2
+150
10
50
2
C
Package Mechanical Details
500 mil x 500 mil CQFP hermetic with gullwing leads
32 pins, 50-mil lead pitch
Alumina body, Kovar lid
mA
mA
A
Table 3. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12, 15, 16, 17,
18, 24, 25, 29
13, 14, 26, 27,
28
19, 20, 21, 22,
23
30
31
32
Paddle
Pin Name
AGND
VREF
EAINP
EAINM
EAOUT
ISET
ICOMP
RSET
SYNCOb
PGOOD
RSEL
GND
V
IN
OUT
SDb
SYNC
SScap
GND
Description
Analog ground
1.000V reference output, loop to
EAINP Additional low pass filtering
may be necessary
Error Amplifier (+) input, loop to VREF
Error Amplifier (–) input, load feedback
Error Amplifier output/loop to ISET
Current Setpoint input/loop to EAOUT
Variable current compensation/
resistor to VOUT
Resistor to set reference current
Loopthrough complement output
Power Good flag output
Reference resistor selection
Input power/signal ground
Input power supply
Switch power output
Shutdown (L)/enable input
Oscillator sync input or int. osc
freq select
Soft Start timing cap input
Ground for proper operation
Exceeding absolute maximum ratings may cause
permanent damage. Operation between maximum
operating ranges and absolute maximum operating
ranges for extended periods may reduce reliability.
Table 6. Electrostatic Discharge (ESD) Ratings
Model
HBM
Parameter/Condition
V
ESD
All pins*
Min
Max
1000
Unit
V
Note: * Human Body Model ESD Voltage (HBM, MIL_STD 883 Method 3015.7)
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Immunity
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
ELDRS
The UltraCMOS process does not exhibit enhanced
low-dose-rate sensitivity (ELDRS) since bipolar
minority carrier elements are not used.
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Technical Data subject to restrictions contained on the cover page.
Product Specification
PE99151
Figure
4.
Die
Pad Layout (Top View)
G
N
D
R
S
E
L
G
N
D
Note: All pin locations originate from the die center and refer to the center of the pin
Table
7.
Die
Pad Coordinates and Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
13
14
Pin
Name
GND
SW
SW
GND
SW
SW
GND
SW
SW
GND
GND
X
1385.9
1366.9
1366.9
1365.9
1366.9
1366.9
1366.9
1366.9
1366.9
1385.9
-1343.9
Y
1433.4
1179.65
810.35
500
189.65
-189.65
-500
-810.35
-1179.65
-1433.4
-1437.25
-1266.9
-1068.3
-869.7
Ground
Switch
Switch
Ground
Switch
Switch
Ground
Switch
Switch
Ground
Switch
Variable Current Compensa-
tion/Resistor to VOUT
Current Set-Point Input/Loop to
EAOUT
Error Amplifier Output/Loop
ISET
21
22
23
24
TCSEL1
GND
CCSEL
EAINM
-1343.9
-1343.9
-1343.9
-1343.9
297.2
500
696.1
869.7
18
19
20
VREFSEL2
VREFSEL3
TCSEL0
-1343.9
-1343.9
-1343.9
-148.7
-0.1
148.5
Description
Pin
No.
15
16
17
Pin Name
VREFSEL0
GND
VREFSEL1
X
-1343.9
-1343.9
-1343.9
Y
-696.1
-500
-297.3
Description
Bandgap Reference
Voltage Fine Adjust (0)
Ground
Bandgap Reference
Voltage Fine Adjust (1)
Bandgap Reference
Voltage Fine Adjust (2)
Bandgap Reference
Voltage Fine Adjust (3)
Bandgap Reference Voltage
Fine Adjust (0)
Bandgap Reference Voltage
Fine Adjust (0)
Ground
Course trim code
Error Amplifier (-) Input,
Loop to VREF
ICOMP -1343.9
ISET
-1343.9
EAOUT -1343.9
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Technical Data subject to restrictions contained on the cover page.
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