FEDL7012-04-01
1
Semiconductor
ML7012-04
2400 bps Single Chip Full Duplex Data Modem with Protocol
This version: Sep. 2000
GENERAL DESCRIPTION
The ML7012-04 is a single chip modem LSI device that enables data communication conforming to ITU-T
recommendations V.22bis, V.22, and V.21. This device is equipped with the error correction protocol function
conforming to MNP Class 4. (The MNP Class 4 can be used for V.22bis or V.22.)
The ML7012-04 consists of high speed DSP, analog front end, and digital logic circuit. In addition, this device
provides local analog loop testing, synchronous/asynchronous switching, dialing, and auto answering functions.
The ML7012-04 has a serial interface as an external interface. When integrated into the system, it is controlled
from a control CPU through a serial interface (e.g. UART). By connecting a level converter, the ML7012-04 can
easily implement a modem that can be controlled through the RS-232C interface.
FEATURES
•
Conforming to ITU-T Recommendations V.22 bis, V.22, and V.21: Asynchronous
•
Error correction function conforming to MNP Class 4
•
Serial interface: V.24 interface
•
AT commands (excluding automatic command speed detection)
•
Terminal data speed between DTE and DCE: 9600 bps, 2400 bps, 1200 bps, 300 bps
•
Character format: 10 bit/character
•
DTMF sending function
•
Pulse-dial control signal output
•
Call progress tone
•
Auto answering function
•
Built-in electronic HYB circuit (a line transformer can be directly coupled)
•
Single +3 V power supply
•
Power consumption: Typ. = 35 mA (V
DD
= 3.3 V)
•
Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: ML7012-04GA)
* MNP is a registered trademark of Microcom Inc.
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FEDL 7012-04-01
1
Semiconductor
ML7012-04
BLOCK DIAGRAM
RLY2
RLY1
RTS
CTS
DCD
DSR
DTR
Control section
CI
STD
SRD
SPEED1, 0
PDN/RST
OSC0
OSC1
To each
section
SG Gen.
Clock
generation
GSR
SG
UART
Tone
generation
–
+
AOUT
Modulation/
demodulation
AFE
RCI
–
+
RCAO
TXAI
TXAN
–
+
TXAP
Tone
detection
–
+
AIN
TST2 to 0
TI8 to 0
TO10 to 0
VDD2, 1
GND2, 1
SPK
RII
V
DDA
GNDA
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FEDL 7012-04-01
1
Semiconductor
ML7012-04
PIN CONFIGURATION (TOP VIEW)
GNDA
50
GND2
RLY2
RLY1
GSR
SRD
STD
CTS
RTS
TO8
V
DD2
AIN
SG
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
NC
DSR
DCD
TO9
TO10
DTR
CI
TI8
TO0
TO1
TO2
SPEED1
SPEED0
TI0
TI1
NC
51
49
NC
RII
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
34
36
35
34
33
TXAP
TXAN
TXAI
RCAO
RCI
AOUT
V
DDA
OSC1
OSC0
TI7
TI6
TI5
NC
PDN/RST
TST0
NC
NC
17
TI2
18
TI3
19
V
DD1
20
TI4
21
SPK
22
TO3
23
TO4
24
NC
25
TO5
26
TO6
27
TO7
28
TST2
29
TST1
30
GND1
31
64-Pin Plastic QFP
Note: Pins marked (NC) are no-connection pins which are left open.
NC
32
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FEDL 7012-04-01
1
Semiconductor
ML7012-04
PIN DESCRIPTIONS
System & Clock
Symbol
OSCO
OSC1
I/O
I
O
Description
Pins to connect crystal, resistors and capacitors for the master clock oscillation. When
supplying the master clock from an external source, use OSC0 and leave OSC1 open.
Master clock frequency = 11.0592 MHz. When
PDN/RST
=
“0”,
OSC1 =
“1”.
Power-down and reset control input pin. When
PDN/RST
=
“0”,
this device is in the
power-down state and internal circuits are reset.
“0”: Power-down state,
“1”:
Normal operation
PDN/RST
After power-on, use this pin after setting it to “0” for 1 µs or more to reset internal
circuits. Waiting for 230 ms or more is required until restarting a normal operation after
reset release.
If this pin remains at “0” after power-on, the internal circuits become undefined and
the power-down current may increase. To avoid this, input
“1”
to this pin and start
oscillation or input the master clock to operate the internal circuits, and then set it to
“0”
I
V.24 Serial Interface
Symbol
STD
SRD
RTS
CTS
DCD
DSR
DTR
CI
I/O
I
O
I
O
O
O
I
O
Description
Send data input pin
Receive data output pin
When
PDN/RST
=
“0”,
SRD outputs
“1”.
RTS (Request to Send) signal input pin
CTS (Clear to Send) signal output pin
When
PDN/RST
=
“0”,
CTS outputs
“1”.
DCD (Data Carrier Detect) signal output pin
When
PDN/RST
=
“0”,
DCD outputs
“1”.
DSR (Data Set Ready) signal output pin
When
PDN/RST
=
“0”,
DSR outputs
“1”.
DTR (Data Terminal Ready) signal input pin
CI (Calling Indicator) signal output pin (*2)
When
PDN/RST
=
“0”,
CI outputs
“1”.
0: Space, 1: Mark
0: Space, 1: Mark
0: On, 1: Off
0: On, 1: Off
0: On, 1: Off
0: On, 1: Off
0: On, 1: Off
0: On, 1: Off
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FEDL 7012-04-01
1
Semiconductor
ML7012-04
Analog Interface
Symbol
AOUT
RCI
RCAO
TXAI
TXAN
TXAP
AIN
GSR
SG
I/O
O
I
O
I
O
O
I
O
O
Transmit analog output pin
When
PDN/RST
=
“0”,
AOUT is in a high impedance state.
Operational amplifier input pin constituting transmit RC active
Operational amplifier output pin constituting transmit RC active
When
PDN/RST
=
“0”,
RCAO is in a high impedance state.
Input pin of the line transformer drive amplifier
Output pin of the line transformer drive amplifier (1)
When
PDN/RST
=
“0”,
TXAN is in a high impedance state.
Output pin of the line transformer drive amplifier (2)
When
PDN/RST
=
“0”,
TXAP is in a high impedance state.
Input pin of the receive input amplifier
Output pin of the receive input amplifier
When
PDN/RST
=
“0”,
GSR is in a high impedance state.
Pin to connect capacitors for the SG circuit
When
PDN/RST
=
“0”,
SG is in a high impedance state.
Description
PSTN Line Control Interface
Symbol
I/O
Description
Off-hook and pulse dial control signal output pin (*1)
RLY1
O
0: On-hook or break state of pulse dial
1: Off-hook or make state of pulse dial
When
PDN/RST
=
“0”,
RLY1 outputs “0”.
The control signal output pin to disconnect interlinked telephones (*1)
RLY2
O
0: PSTN is connected with interlinked telephones
1: PSTN is disconnected with interlinked telephones but connected with modem
When
PDN/RST
=
“0”,
RLY2 outputs “0”.
Incoming signal input pin (*2)
RII
I
Input
“0”
while detecting an incoming signal
Input
“1”
while not detecting an incoming signal
Fix this pin to "1" when a ring detector is not used.
Speaker control signal output pin
SPK
O
0: speaker On
1: speaker Off
When
PDN/RST
=
“0”,
SPK outputs
“1”.
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