ATT3030-125H68I datasheet, PDF

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ATT3030-125H68I: DescriptionField-Programmable Gate Arrays; File Size519KB，80 Pages; ManufacturerETC

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Field-Programmable Gate Arrays

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Data Sheet

February 1997

ATT3000 Series Field-Programmable Gate Arrays

Features

Description

The CMOS ATT3000 Series Field-Programmable

Gate Array (FPGA) family provides a group of high-

density, digital integrated circuits. Their regular,

extendable, ﬂexible, user-programmable array

architecture is composed of a conﬁguration program

store plus three types of conﬁgurable elements: a

perimeter of I/O blocks, a core array of logic blocks,

and resources for interconnection. The general struc-

ture of an FPGA is shown in Figure 1.

The

ORCA

Foundry for ATT3000 Development Sys-

tem provides automatic place and route of netlists.

Logic and timing simulation are available as design

veriﬁcation alternatives. The design editor is used for

interactive design optimization and to compile the

data pattern that represents the conﬁguration pro-

gram.

The FPGA’s user-logic functions and interconnec-

tions are determined by the conﬁguration program

data stored in internal static memory cells. The pro-

gram can be loaded in any of several modes to

accommodate various system requirements. The

program data resides externally in an EEPROM,

EPROM, or ROM on the application circuit board, or

on a ﬂoppy disk or hard disk. On-chip initialization

logic provides for optional automatic loading of pro-

gram data at powerup. A serial conﬁguration PROM

can provide a very simple serial conﬁguration pro-

gram storage.

Xilinx, XC3000,

and

XC3100

are registered trademarks of

Xilinx, Inc.

High performance:

— Up to 270 MHz toggle rates

— 4-input LUT delays <2.7 ns

User-programmable gate arrays

— Unlimited reprogrammability

— Easy design iteration through in-system

logic changes

Flexible array architecture:

— Compatible arrays ranging from 1500 to

6000 gate logic complexity

— Extensive register, combinatorial, and I/O

capabilities

— Low-skew clock nets

— High fan-out signal distribution

— Internal 3-state bus capabilities

— TTL or CMOS input thresholds

— On-chip oscillator ampliﬁer

Standard product availability:

— Low-power 0.55 µm CMOS, static memory

technology

— Pin-for-pin compatible with

Xilinx* XC3000*

and

XC3100*

families

— Cost-effective for volume production

— 100% factory pretested

— Selectable conﬁguration modes

ORCA™

Foundry for ATT3000 Development

System support

All FPGAs processed on a QML-certiﬁed line

Extensive packaging options

Table 1. ATT3000 Series FPGAs

FPGA

ATT3020

ATT3030

ATT3042

ATT3064

ATT3090

Max

Logic

Gates

1,500

2,000

3,000

4,500

6,000

Typical Gate

Range

1,000—1,500

1,500—2,000

2,000—3,000

3,500—4,500

5,000—6,000

Conﬁgurable

Logic

Blocks

100

144

224

320

Array

8x8

10 x 10

12 x 12

16 x 14

20 x 16

User I/Os

Max

120

144

Flip-

Flops

256

360

480

688

928

Horizontal

Long Lines

Conﬁguration

Data Bits

14,779

22,176

30,784

46,064

64,160

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