Integrated
Circuit
Systems, Inc.
AV9110
Serially Programmable Frequency Generator
General Description
The
AV9110
generates user specified clock frequencies using
an externally generated input reference, such as 14.318 MHz
or 10.00 MHz crystal connected between pins 1 and 14.
Alternately, a TTL input reference clock signal can be used.
The output frequency is determined by a 24-bit digital word
entered through the serial port. The serial port enables the
user to change the output frequency on-the-fly.
The clock outputs utilize CMOS level output buffers that
operate up to 130 MHz.
Features
•
•
•
•
•
•
•
•
•
Complete user programmability of output frequency
through serial input data port
On-chip Phase-Locked Loop for clock generation
Generates accurate frequencies up to 130 MHz
Tristate CMOS outputs
5 volt power supply
Low power CMOS technology
14-pin DIP or 150-mil SOIC
Very low jitter
Wide operating range VCO
Applications
Graphics: The
AV9110
generates low jitter, high speed pixel
(or dot) clocks. It can be used to replace multiple expensive
high speed crystal oscillators. The flexibility of this device
allows it to generate nonstandard graphics clocks, allowing
the user to program frequencies on-the-fly.
Block Diagram
9110 Rev F 5/30/00
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
AV9110
Pin Configuration
Clock Reference Implementations:
AV9110-01 vs. AV9110-02
The
AV9110
requires a stable reference clock (5 to 32 MHz) to
generate a stable, low jitter output clock. The
AV9 11 0 -01
is
optimized to use an external quartz crystal as a frequency
reference, without the need of additional external components.
The AV9110-02 is optimized to accept an TTL clock
reference. Either device can be used with an external crystal
or accept a TTL clock reference, although extra components
may be required. The various combinations implied are
summarized in Figure 2 (see page 7).
14 Pin Dip, SOIC
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P I N NA M E
X1
AV D D
AGND
VDD
GND
DATA
SCLK
CE#
CLK/X
GND
VDD
CLK
OE
X2
PIN
TYPE
Input
P ow e r
P ow e r
P ow e r
P ow e r
Input
Input
Input
Output
P ow e r
Power
Output
Input
Output
DESCRIPTION
Crystal input or TTL reference clock.
ANALOG power supply. Connect to +5V.
ANALOG GROUND.
Digital power supply. Connect to +5V.
Digital GROUND.
Serial DATA pin.
SERIAL CLOCK. Clocks shift register.
CHIP ENABLE. Active low, controls data transfer.
CMOS CLOCK divided by X output.
Digital GROUND.
Digital power supply. Connect to +5V.
CMOS CLOCK output.
OUTPUT ENABLE. Tristates both outputs when low.
Crystal input or TTL reference clock.
2
AV9110
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Voltage on I/O pins referenced to GND . . . . . . GND –0.5 V to V
DD
+0.5 V
Operating Temperature under bias . . . . . . . . . . 0°C to +70°C
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . 0.8 Watts
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics
V
DD
= +5V±10%, T
A
= 0 – 70
°
C unless otherwise stated
DC/STATIC
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
1
Output High Voltage
1
Input Clock Rise Time
1
Input Clock Fall Time
1
Supply Current
SYMBOL
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
OH
= 8Ma
I
CLKr
I
CLKf
I
DD
f
o
t
r
t
f
d
t
25pF load
25pF load
25pF load
No load
AC/DYNAMIC
Output frequency range
Rise time, 20-80%
1
Fall time, 80-20%
1
Duty cycle
1
@ 50%
Jitter, 1 sigma
1
Jitter, absolute
1
Input reference freq.; AV9110-01
1
Input reference freq.; AV9110-02
1
Input DATA or SCLK frequency
1
Skew, Output to Output/X1
f
REF
f
REF
f
DATA
t
skew
Crystal input
TTL input
0.78
-
-
40
-
-
5
0.6
-
-
-
-
-
-
±40
±125
14.318
14.318
-
400
130
3
3
60
-
-
32
32
32
-
MHz
ns
ns
%
ps
ps
MHz
MHz
MHz
ps
TEST CONDITIONS
V
DD
= 5V
V
DD
= 5V
V
IN
= OV
V
IN
= VDD
I
OL
= 8Ma
MIN
-
2.0
-
-
-
2.4
-
-
-
TYP
-
-
-
-
-
-
-
-
25
MAX
0.8
-
-5
5
0.4
-
20
20
-
UNITS
V
V
µA
µA
V
V
ns
ns
mA
Note 1:
Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
AV9110
Serial Programming
The
AV9110
is programmed to generate clock frequencies by
entering data through the shift register. Figure 1 displays the
proper timing sequence. On the negative going edge of CE#,
the shift register is enabled and the data at the DATA pin is
loaded into the shift register on the rising edge of the SCLK.
Bit D0 is loaded first, followed by D1, D2, etc. This data
consists of the 24 bits shown in the Shift Register Bit
Assignment in Table 1, and therefore takes 24 clock cycles to
load. An internal counter then disables the input and transfers
the data to internal latches on the rising edge of the 24th
cycle of the SCLK. Any data entered after the 24th cycle is
ignored until CE# must remain low for a minimum of 24 SLCK
clock cycles. If CE# is taken high before 24 clock cycles have
elapsed, the data is ignored (no frequency change occurs)
and the counter is reset. Tables 1 and 2 display the bit location
for generating the output clock frequency and the output
divider circuitry, respectively.
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
ASSIGNMENT
VCO frequency divider (LSB)
VCO frequency divider
VCO frequency divider
VCO frequency divider
VCO frequency divider
VCO frequency divider
VCO frequency divider (MSB)
Reference frequency divider (LSB)
Reference frequency divider
Reference frequency divider
Reference frequency divider
Reference frequency divider
Reference frequency divider
Reference frequency divider (MSB)
VCO pre-scale divide (0=divide by 1, 1=divide by 8
CLK/X output divide COD0 (see Table 2)
CLK/X output divide COD1 (see Table 2)
VCO output divide VOD0 (see Table 3)
VCO output divide VOD1 (see Table 3)
Outplut enable CLK (0=tristate)
Output enable CLK/X (0=tristate)
Reserved. Should be programmmed high (1)
Reference clock select on CLK (1 = reference frequency)
Reserved. Should be programmed high (1)
EQUATION
VARIABLE
DEFAULT
-01
1
1
1
1
1
1
1
0
1
0
0
1
0
0
-02
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
1
0
0
1
1
1
1
0
1
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
N
Integer
M
Integer
V
X
R
0
0
1
0
1
1
1
1
0
1
4
AV9110
Output Divider Turth Tables
Table 2
COD1
0
0
1
1
COD0
0
1
0
1
CLK/X
Output Divide
(X)
1
2
4
8
COD1
0
0
1
1
Table 3
COD0
0
1
0
1
VCO
Output Divide
(R)
1
2
4
8
Programming the PLL
The AV9110 has a wide operating range but it is recommended that it is operated within the following limits:
2 MHz < f
REF
< 32 MHz
200 kHz <
f
REF
= Input reference frequency
M = Reference divide, 3 to 127
f
VCO
= VCO output frequency
f
CLK
= CLK or CLK/X output frequency
f
REF
< 5MHz
M
50 MHz < f
VCO
<250 MHz
f
VCO
< 250 MHz
The AV9110 is a classical PLL circuit and the VCO output frequency is given by:
f
VCO
=
N•V• fREF
M
Where N = VCO divided, 3 to 127
M =m Reference divide, 3 to 127
V = Perscale, 1 or 8
The 2 output drivers then give the following frequencies:
f
CLK
=
f
VCO
R
f
CLK/X
=
f
VCO
R•X
= N•V• fREF
MR
=
f
VCLK
X
or f
REF
(output mixable by bit 17)
Where R, X = output dividers 1, 2, 4 or 8
Notes:
1. Output frequency accuracy will depend solely on input reference frequency accuracy.
2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or greater. This will
give improved duty cycle.
3. The minimum output frequency step size is approximately 0.2% due to the divider range provided.
5
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