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ICS9112-28

Description
Preliminary Product Preview
File Size83KB,3 Pages
ManufacturerICS ( IDT )
Websitehttp://www.icst.com
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ICS9112-28 Overview

Preliminary Product Preview

Integrated
Circuit
Systems, Inc.
ICS9112-28
Preliminary Product Preview
Low Skew Output Buffer
General Description
The
ICS9112-28
is a high performance, low skew, low jitter
clock driver. It is designed to distribute high speed clocks in
PC systems operating at speeds from 0 to 133 MHz.
The
ICS9112-28
comes in an eight pin 150 mil SOIC package.
It has four output clocks.
Features
Frequency range 0 - 133 MHz (3.3V)
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC &
173 mil TSSOP packages.
3.3V ±10% operation
Block Diagram
CLK0
CLK1
CLK_IN
CLK2
Pin Configuration
CLK_IN
CLK0
GND
CLK1
1
2
3
4
ICS9112-28
8
7
6
5
CLK4
VDD
CLK3
CLK2
8 pin SOIC
CLK3
CLK4
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
PIN NAME
CLK_IN
CLK0
1
GND
CLK1
1
CLK2
1
CLK3
1
VDD
CLK4
1
TYPE
IN
OUT
PWR
OUT
OUT
OUT
PWR
OUT
Input reference frequency.
Buffered clock output
Ground
Buffered clock output
Buffered clock output
Buffered clock output
Power Supply (3.3V)
Buffered clock output
DESCRIPTION
Notes:
1. Weak pull-down on all outputs
9112-28 Rev B 01/09/06
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

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