Integrated
Circuit
Systems, Inc.
ICS853111A
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
F
EATURES
•
10 differential 2.5V/3.3V LVPECL / ECL outputs
•
2 selectable differential input pairs
•
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•
Maximum output frequency: >3GHz
•
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
•
Output skew: 23ps (typical)
•
Part-to-part skew: 85ps (typical)
•
Propagation delay: 705ps (typical)
•
Jitter, RMS: < 0.03ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 5.25V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -5.25V to -2.375V
•
-40°C to 85°C ambient operating temperature
•
Pin compatible with MC100EP111 and MC100LVEP111
G
ENERAL
D
ESCRIPTION
The ICS853111A is a low skew, high perfor-
mance 1-to-10 Differential-to-2.5V/3.3V LVPECL/
HiPerClockS™
ECL Fanout Buffer and a member of the
HiPerClockS ™ family of High Performance
Clock Solutions from ICS. The ICS853111A
is characterized to operate from either a 2.5V, 3.3V or a
5V power supply. Guaranteed output and par t-to-par t
skew characteristics make the ICS853111A ideal for
those clock distribution applications demanding well de-
fined performance and repeatability.
ICS
B
LOCK
D
IAGRAM
PCLK0
nPCLK0
PCLK1
nPCLK1
0
1
P
IN
A
SSIGNMENT
nQ3
nQ4
nQ5
Q1
nQ1
V
CCO
Q2
nQ2
nQ2
Q2
25
26
27
28
29
30
31
32
24 23 22 21 20 19 18 17
16
15
14
V
CCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
V
CCO
CLK_SEL
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
nQ1
Q1
nQ0
Q0
V
CCO
nQ6
Q3
Q4
Q5
Q6
Q0
nQ0
ICS853111A
13
12
11
10
9
V
BB
1
V
CC
2
CLK_SEL
3
PCLK0
4
nPCLK0
5
VBB
6
PCLK1
7
nPCLK1
8
V
EE
REV. B MAY 14, 2004
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
853111AY
www.icst.com/products/hiperclocks.html
1
Integrated
Circuit
Systems, Inc.
ICS853111A
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
Type
Description
Core supply pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.
When LOW, selects PCLK0, nPCLK0 inputs.
LVCMOS / LVTTL interface levels.
Non-inver ting differential clock input.
Inver ting differential LVPECL clock input.
V
CC
/2 default when left floating.
Bias voltage.
Pulldown
Pullup/Pulldown
Non-inver ting differential clock input.
Inver ting differential LVPECL clock input.
V
CC
/2 default when left floating.
Negative supply pin.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
Name
V
CC
CLK_SEL
PCLK0
nPCLK0
V
BB
PCLK1
nPCLK1
V
EE
V
CCO
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Power
Input
Input
Input
Output
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pulldown
Pulldown
Pullup/Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
VCC/
2
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
KΩ
KΩ
T
ABLE
3A. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
PCLKx
0
1
0
1
nPCLKx
1
0
Biased;
NOTE 1
Biased;
NOTE 1
Outputs
Q0:Q9
LOW
HIGH
LOW
HIGH
nQ0:Q9
HIGH
LOW
HIGH
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
T
ABLE
3B. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_SEL
0
1
Selected Source
PCLK0, nPCLK0
PCLK1, nPCLK1
Biased;
0
HIGH
LOW
Single Ended to Differential
Inver ting
NOTE 1
Biased;
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to
Accept Single Ended Levels".
853111AY
www.icst.com/products/hiperclocks.html
2
REV. B MAY 14, 2004
Integrated
Circuit
Systems, Inc.
ICS853111A
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
6V (LVPECL mode, V
EE
= 0)
-6V (ECL mode, V
CC
= 0)
-0.5V to V
CC
+ 0.5 V
0.5V to V
EE
- 0.5V
50mA
100mA
± 0.5mA
-65°C to 150°C
37.8°C/W (0 lfpm)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
V
BB
Sink/Source, I
BB
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40°C to +85°C
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V; V
EE
= 0V
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
5.25
85
Units
V
mA
T
ABLE
4B. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended)
Input Low Voltage
(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
PCLK0, PCLK1
Input
Low Current nPCLK0, nPCLK1
Min
2.175
1.405
2.075
1.43
1.86
150
1.2
800
-40°C
Typ
2.275
1.545
Max
2.38
1.68
2.36
1.765
1.98
1200
3.3
150
Min
2.225
1.425
2.075
1.43
1.86
150
1.2
25°C
Typ
2.295
1.52
Max
2.37
1.615
2.36
1.765
1.98
Min
2.295
1.44
2.075
1.43
1.86
150
1.2
85°C
Typ
2.33
1.535
Max
2.365
1.63
2.36
1.765
1.98
Units
V
V
V
V
V
800
1200
3.3
150
800
1200
3.3
150
m
V
V
µA
µA
µA
-10
-150
-10
-150
-10
-150
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Single-ended input operation is limited. V
CC
≥
3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V
IH
.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is V
CC
+ 0.3V.
853111AY
www.icst.com/products/hiperclocks.html
3
REV. B MAY 14, 2004
Integrated
Circuit
Systems, Inc.
ICS853111A
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
-40°C
Min
1.375
0.605
1.275
0.63
150
1.2
800
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V; V
EE
= 0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended)
Input Low Voltage
(Single-Ended)
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
Input
Low Current
PCLK0, PCLK1
25°C
Max
1.58
0.88
1.56
0.965
1200
2.5
150
-10
-10
85°C
Max
1.57
0.815
1.56
0.965
Typ
1.475
0.745
Min
1.425
0.625
1.275
0.63
150
1.2
Typ
1.495
0.72
Min
1.495
0.64
1.275
0.63
150
1.2
Typ
1.53
0.735
Max
1.565
0.83
Units
V
V
V
V
-0.83
0.965
800
1200
2.5
150
800
1200
2.5
150
m
V
V
µA
µA
µA
-10
-150
-150
-150
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is V
CC
+ 0.3V.
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 5V; V
EE
= 0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended)
Input Low Voltage
(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
PCLK0, PCLK1
Input
Low Current nPCLK0, nPCLK1
Min
3.875
3.105
3.775
3.13
3.56
150
1.2
800
-40°C
Typ
3.975
3.245
Max
4.08
3.38
4.06
3.465
3.68
1200
5
150
Min
3.925
3.125
3.775
3.13
3.56
150
1.2
25°C
Typ
3.995
3.22
Max
4.07
3.315
4.06
3.465
3.68
Min
3.995
3.14
3.775
3.13
3.56
150
1.2
85°C
Typ
4.03
3.235
Max
4.065
3.33
4.06
3.465
3.68
Units
V
V
V
V
V
800
1200
5
150
800
1200
5
150
m
V
V
µA
µA
µA
-10
-150
-10
-150
-10
-150
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Single-ended input operation is limited. V
CC
≥
3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V
IH
.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is V
CC
+ 0.3V.
853111AY
www.icst.com/products/hiperclocks.html
4
REV. B MAY 14, 2004
Integrated
Circuit
Systems, Inc.
ICS853111A
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
-40°C
Min
-1.125
-1.895
-1.225
-1.87
-1.44
150
V
EE
+1.2V
800
T
ABLE
4C. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.25V
TO
-2.375V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended)
Input Low Voltage
(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
Input
Low Current
PCLK0, PCLK1
25°C
Max
-0.92
-1.62
-0.94
-1.535
-1.32
1200
0
150
-10
-10
85°C
Max
-0.93
-1.685
-0.94
-1.535
-1.32
Typ
-1.025
-1.755
Min
-1.075
-1.875
-1.225
-1.87
-1.44
150
V
EE
+1.2V
Typ
-1.005
-1.78
Min
-1.005
-1.86
-1.225
-1.87
-1.44
150
V
EE
+1.2V
Typ
-0.97
-1.765
Max
-0.935
-1.67
-0.94
-1.535
-1.32
Units
V
V
V
V
V
800
1200
0
150
800
1200
0
150
m
V
V
µA
µA
µA
-10
-150
-150
-150
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Single-ended input operation is limited. V
CC
≥
3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V
IH
.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is V
CC
+ 0.3V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.25V
TO
-2.375V
OR
V
CC
= 2.375V
TO
5.25V; V
EE
= 0V
Symbol
f
MAX
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
20% to 80%
85
570
-40°C
Min
Typ
>3
670
23
85
0.03
200
315
100
770
35
150
605
Max
Min
25°C
Typ
>3
705
23
85
0.03
200
285
85
805
35
150
665
Max
Min
85°C
Typ
>3
765
23
85
0.03
200
315
875
35
150
Max
Units
GHz
ps
ps
ps
ps
ps
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
/t
F
All parameters are measured
≤
1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853111AY
www.icst.com/products/hiperclocks.html
5
REV. B MAY 14, 2004
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