Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
F
EATURES
•
12 LVCMOS / LVTTL outputs
•
LVCMOS / LVTTL clock input
•
Maximum output frequency: 250MHz
•
Output skew: 160ps (maximum)
•
Operating supply modes: Core/Output
3.3V/3.3V
2.5V/2.5V
1.8V/1.8V
3.3V/2.5V
3.3V/1.8V
2.5V/1.8V
•
-40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8312I is a low skew, 1-to-12 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockS™
HiPerClockS™family of High Performance Clock
Solutions from ICS. The ICS8312I single ended
clock input accepts LVCMOS or LVTTL input lev-
els. The low impedance LVCMOS outputs are designed to
drive 50Ω series or parallel terminated transmission lines. The
effective fanout can be increased from 12 to 24 by utilizing
the ability of the outputs to drive two series terminated lines.
ICS
The ICS8312I is characterized at full 3.3V, 2.5V, and 1.8V, or
mixed 3.3V core/2.5V, 3.3V core/1.8V and 2.5V core/1.8V out-
put operating supply modes. Guaranteed output and part-to-
part skew characteristics along with the 1.8V output capa-
bilities makes the ICS8312I ideal for high performance, single
ended applications that also require a limited output voltage.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
GND
GND
V
DDO
V
DDO
Q0
Q1
Q2
Q3
CLK_EN
nD
Q
LE
12
GND
V
DD
Q0:Q11
CLK_EN
CLK
GND
OE
V
DD
GND
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
Q4
V
DDO
Q5
GND
Q6
V
DDO
Q7
GND
CLK
ICS8312I
21
20
19
18
17
OE
9 10 11 12 13 14 15 16
Q11
V
DDO
Q10
GND
Q9
V
DDO
Q8
GND
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Pacakge
Top View
8312AYI
http://www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 23, 2003
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
Type
Power
Power
Input
Input
Input
Description
Power supply ground.
Core supply pins.
Synchronous control for enabling and disabling clock outputs.
Pullup
LVCMOS / LVTTL interface levels.
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs
Pullup
Q0 thru Q11. LVCMOS / LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 5, 8, 12,
16, 17, 21,
25, 29
2, 7
3
4
6
Name
GND
V
DD
CLK_EN
CLK
OE
9, 11, 13, 15,
Q11, Q10, Q9, Q8,
18, 20, 22,
Q7, Q6, Q5,
Output
Q0 thru Q11 outputs. LVCMOS / LVTTL interface levels.
24, 26, 28,
Q4, Q3, Q2,
30, 32
Q1, Q0
10, 14, 19,
Power
Output supply pins.
V
DDO
23, 27, 31
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
V
DDO
= 3.3V ± 5%
Output Impedance
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 2V
51
51
7
7
10
Test Conditions
Minimum
Typical
Maximum
4
19
18
16
Units
pF
pF
pF
pF
KΩ
KΩ
Ω
Ω
Ω
T
ABLE
3A. O
UTPUT
E
NABLE
Control Inputs
OE
0
1
1
AND
C
LOCK
E
NABLE
F
UNCTION
T
ABLE
Output
Q0:Q11
Hi-Z
LOW
Follows CLK input
CLK_EN
X
0
1
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
OE
1
1
8312AYI
Outputs
CLK
0
1
Q0:Q11
LOW
HIGH
http://www.icst.com/products/hiperclocks.html
2
REV. A OCTOBER 23, 2003
CLK_EN
1
1
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
10
10
Units
V
V
µA
µA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Symbol
V
DD
V
DDO
I
DD
I
DDO
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
10
10
Units
V
V
µA
µA
Units
V
V
µA
µA
Units
V
V
µA
µA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Test Conditions
Minimum
1.6
1.6
Typical
1.8
1.8
Maximum
2.0
2.0
10
10
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
10
10
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
T
ABLE
4E. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Symbol
V
DD
V
DDO
I
DD
I
DDO
8312AYI
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
10
10
Units
V
V
µA
µA
Units
V
V
µA
µA
T
ABLE
4F. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Test Conditions
Minimum
2.375
1.6
Typical
2.5
1.8
Maximum
2.625
2.0
10
10
http://www.icst.com/products/hiperclocks.html
3
REV. A OCTOBER 23, 2003
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
Test Conditions
V
DD
= 3.3V ± 5%
CLK
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
DD
= 3.3V ± 5%
CLK_EN, OE
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
DD
= 3.3V ± 5%
CLK
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
DD
= 3.3V ± 5%
CLK_EN, OE
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
DD
= 3.3V ± 5%
CLK
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
DD
= 3.3V ± 5%
CLK_EN, OE
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
DD
= 3.3V ± 5%
CLK
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
DD
= 3.3V ± 5%
CLK_EN, OE
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
DDO
= 3.3V ± 5%; NOTE 1
V
DDO
= 2.5V ± 5%; I
OH
= -1mA
-5
-5
-5
-150
-150
-150
2.6
2
1.8
V
DD
- 0.2
V
DD
- 0.3
0.5
0.4
0.45
0.2
0.35
Minimum
2
1.7
0.65*V
DD
2
1.7
0.65*V
DD
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
1.3
0.7
0.35*V
DD
1.3
0.7
0.35*V
DD
150
150
150
5
5
5
Units
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
V
V
T
ABLE
4F. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40°C
TO
85°C
Symbol
Parameter
V
IH
Input High Voltage
V
IL
Input Low Voltage
I
IH
Input High Current
I
IL
Input Low Current
V
OH
Output High Voltage
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; I
OH
= -100uA
V
DDO
= 1.8V ± 0.2V; NOTE 1
V
DDO
= 3.3V ± 5%; NOTE 1
V
DDO
= 2.5V ± 5%; I
OL
= 1mA
V
OL
Output Low Voltage
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; I
OL
= 100uA
V
DDO
= 1.8V ± 0.2V; NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
8312AYI
http://www.icst.com/products/hiperclocks.html
4
REV. A OCTOBER 23, 2003
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
Test Conditions
f
≤
250MHz
Minimum
Typical
Maximum Units
250
1.2
2.0
2.7
150
850
20% to 80%
f
≤
150MHz
175
45
800
55
MHz
ns
ps
ps
ps
%
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
Par t-to-Par t Skew; NOTE 3, 5
Output Rise Time; NOTE 4
Output Duty Cycle
t
sk(o)
t
sk(pp)
t
R
/t
F
odc
All parameters measured at f
MAX
unless noted otherwise.
See Table 5C listed below for Notes 1 through 5.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
Par t-to-Par t Skew; NOTE 3, 5
Output Rise Time; NOTE 4
Output Duty Cycle
20% to 80%
f
≤
150MHz
200
45
f
≤
250MHz
1.25
2.4
Test Conditions
Minimum
Typical
Maximum Units
250
3.5
155
1.1
800
55
MHz
ns
ps
ns
ps
%
t
sk(o)
t
sk(pp)
t
R
/t
F
odc
All parameters measured at fMAX unless noted otherwise.
See Table 5C listed below for Notes 1 through
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
Par t-to-Par t Skew; NOTE 3, 5
Output Rise Time; NOTE 4
Output Duty Cycle
20% to 80%
f
≤
100MHz
175
45
f
≤
200MHz
1.6
3.3
Test Conditions
Minimum
Typical
Maximum Units
200
4.9
160
2.4
875
55
MHz
ns
ps
ns
ps
%
t
sk(o)
t
sk(pp)
t
R
/t
F
odc
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8312AYI
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5
REV. A OCTOBER 23, 2003
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