Si5344H/42H Rev D
H
I G H
-F
R E Q U E N C Y
, U
LTRA
-L
O W
J
I T T E R
A
T T E N U A T O R
C
L O C K
W I T H
D
IG ITA LLY
- C
O N T R O L L E D
O
S C I L L A T O R
Features
High-speed outputs generate an
ultra-low jitter output up to 2.75 GHz
Up to four Multi-Synth outputs
generate any frequency up to
717.5 MHz
Input frequency range:
8 kHz to 750 MHz
Maximum Output frequency:
High-Frequency Mode: 2.75 GHz
MultiSynth Mode: 717.5 MHz
Jitter performance:
High Frequency Mode:
<50 fs typ (1 MHz–40 MHz)
MultiSynth Mode:
<150 fs typ (12 kHz–20 MHz)
Programmable jitter attenuation
bandwidth: 10 Hz to 4 kHz
Highly configurable outputs
compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with
programmable voltage swing and
common mode
LVPECL-only in High Frequency
Mode
Status monitoring (LOS, OOF, LOL)
Hitless input clock switching:
automatic or manual
Automatic free-run and holdover
modes
Glitchless on the fly output
frequency changes
Locks to gapped clock inputs
DCO mode: as low as 0.001 ppb
steps.
Core voltage
V
DD
: 1.8 V ±5%
V
DDA
:
3.3 V ±5%
Independent output supply pins:
3.3 V, 2.5 V, or 1.8 V
Serial interface: I
2
C or SPI
In-circuit programmable with
non-volatile OTP memory
ClockBuilder Pro
TM
software
simplifies device configuration
Si5342H: 2 input, 2 output, QFN44
Si5344H, 2 input, 4 output, QFN44
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
Ordering Information:
See Section 7.
Pin Assignments
Si5342H 44QFN
Top View
I2C_SEL
RSVD_GND
VDDS
34
NC
VDD
IN0
IN0
NC
VDD
NC
36
44
43
42
41
40
39
38
37
IN1
IN1
IN_SEL0
X1
XA
XB
X2
VDDA
35
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
INTR
VDD
LOS1
LOS0
VDDS
LOS_XAXB
LOL
VDDS
OUT1
OUT1
VDDO1
Applications
GND
Pad
29
28
27
26
25
24
23
100G/200G/400G Optical
Transceivers
Wireless base-stations
VDDA
NC
NC
OUT0
VDD
OE
SDA/SDIO
A1/SDO
A0/CS
RST
OE
SDA/SDIO
A1/SDO
A0/CS
Rev. 1.0 9/16
Copyright © 2016 by Silicon Laboratories
VDDO0
OUT0
SCLK
OUT0
VDD
RST
NC
This specialized jitter attenuating clock multiplier combines fourth-generation
DSPLL with ultra-low phase jitter and MultiSynth™ technologies to enable high
data rate coherent optical transceiver design. Up to four outputs can be assigned
to High Frequency Mode capable of up to 2.75 GHz at 50 fs-rms typical phase
jitter (1 MHz-40 MHz). Each output may also be configured as MultiSynth Mode
any-frequency outputs when added frequency flexibility is required, such as
clocking Forward Error Correction (FEC) while still delivering <150 fs-rms typical
phase jitter (12 kHz-20 MHz). The Si5344H and Si5342H also feature DCO-
control with as low as 0.001 ppb step control and locks to gapped clock inputs.
These devices are programmable via a serial interface with in-circuit
programmable non-volatile memory (NVM) so that they always power up with a
known frequency configuration. The loop filter is fully integrated on-chip
eliminating the risk of potential noise coupling associated with discrete solutions.
Programming the Si5342H/44H is made easy with Silicon Labs’
ClockBuilderPro
software. Factory preprogrammed devices are also available.
Si5344H 44QFN
Top View
I2C_SEL
IN_SEL1
VDDO3
34
VDDO0
OUT0
SCLK
Description
OUT3
36
44
43
42
41
40
39
38
37
IN1
IN1
IN_SEL0
XGND
XA
XB
XGND
VDDA
VDDA
NC
NC
35
OUT3
NC
VDD
IN0
IN0
NC
VDD
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
INTR
VDD
OUT2
OUT2
VDDO2
LOS_XAXB
LOL
VDDS
OUT1
OUT1
VDDO1
GND
Pad
29
28
27
26
25
24
23
Si5344H/42H
Si5344H/42H
T
ABLE
O
F
C
ON TENTS
1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.5. Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.6. Inputs (IN0, IN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.13. Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for
Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.1. Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
8.1. 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
11. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2
Rev. 1.0
Si5344H/42H
1. Typical Application Schematic
Transmit SoC
MUX
Digital
Signal
Processor
DAC
Optical
Front‐
End
Si5344H
Recovered
Clock
DSPLL
Multi‐
Synth
÷
÷
RX DCO
CONTROL
Multi‐
Synth
DMUX
Digital
Signal
Processor
ADC
Optical
Front‐
End
Receive SoC
SPI Interface
Figure 1. 100G/400G Coherent Optical Transceiver Application Example
Rev. 1.0
3
Si5344H/42H
2. Electrical Specifications
Table 1. Recommended Operating Conditions*
(V
DD
= 1.8 V ±5%, V
DDA
= 3.3 V ±5%,T
A
= –40 to 85 °C)
Parameter
Ambient Temperature
Junction Temperature
Core Supply Voltage
Symbol
T
A
TJ
MAX
V
DD
V
DDA
V
DDO
Min
–40
—
1.71
3.14
3.14
2.38
1.71
Typ
25
—
1.80
3.30
3.30
2.50
1.80
3.30
1.80
Max
85
125
1.89
3.47
3.47
2.62
1.89
3.47
1.89
Unit
°C
°C
V
V
V
V
V
V
V
Clock Output Driver Supply Voltage
Status Pin Supply Voltage
V
DDS
3.14
1.71
*Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
4
Rev. 1.0
Si5344H/42H
Table 2. DC Characteristics
Parameter
Core Supply Current
(V
DD
= 1.8 V ±5%, V
DDA
= 3.3 V ±5%, V
DDO
= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T
A
= –40 to 85 °C)
Symbol
I
DD
I
DDA
I
DDOx
Test Condition
Si5342H
Si5344H
High-Frequency Output
Mode (AC-coupled)
@2.75GHz
LVPECL Output
@ 156.25 MHz
LVDS Output
@ 156.25 MHz
3.3 V LVCMOS output
@ 156.25 MHz
2.5 V LVCMOS output
@ 156.25 MHz
1.8 V LVCMOS output
@ 156.25 MHz
Min
—
—
—
Typ
145
120
45
Max
190
125
51
Unit
mA
mA
mA
Output Buffer Supply Current
—
—
—
—
—
—
—
22
15
22
18
12
900
800
26
18
30
23
16
1000
900
mA
mA
mA
mA
mA
mW
mW
Total Power Dissipation
P
d
Si5344H
Si5342H
Notes 1, 5
Notes 2, 5
Notes:
1.
Si5344H test configuration: 2 x 2.5 V LVDS outputs @ 156.25 MHz, 2 x 2.5 V Differential High-Speed Output Mode
(ac-coupled) @ 2.104658 GHz. Excludes power in termination resistors.
2.
Si5342H test configuration: 1 x 2.5 V LVDS output @ 156.25 MHz, 1 x 2.5 V Differential High-Speed Output Mode (ac-
coupled) @ 2.104658 GHz. Excludes power in termination resistors.
3.
Differential outputs terminated into an ac-coupled 100
load.
4.
LVCMOS outputs measured into a 6 inch 50
PCB trace with 5 pF load. Measurements were made in CMOS3 mode.
Differential Output Test Configuration
I
DDO
OUT
OUT
50
0.1 uF
50
0.1 uF
100
I
DDO
OUTa
OUTb
LVCMOS Output Test Configuration
6 inch
50
5 pF
5.
Detailed power consumption for any configuration can be estimated using
ClockBuilder Pro
when an evaluation board
(EVB) is not available. All EVBs support detailed current measurements for any configuration.
Rev. 1.0
5
京公网安备 11010802033920号
EEWORLD
