CD82C37A-5 datasheet, PDF - EEWORLD Datasheet

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CD82C37A-5: Description4 CHANNEL(S), 5 MHz, DMA CONTROLLER, CDIP40; Categorysemiconductor The embedded processor and controller; File Size1000KB，26 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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CD82C37A-5 Overview

4 CHANNEL(S), 5 MHz, DMA CONTROLLER, CDIP40

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DATASHEET

82C37A

CMOS High PerformanceProgrammable DMA Controller

The 82C37A is an enhanced version of the industry standard

8237A Direct Memory Access (DMA) controller, fabricated

using Intersil’s advanced 2 micron CMOS process. Pin

compatible with NMOS designs, the 82C37A offers

increased functionality, improved performance, and

dramatically reduced power consumption. The fully static

design permits gated clock operation for even further

reduction of power.

The 82C37A controller can improve system performance by

allowing external devices to transfer data directly to or from

system memory. Memory-to-memory transfer capability is

also provided, along with a memory block initialization

feature. DMA requests may be generated by either hardware

or software, and each channel is independently

programmable with a variety of features for flexible

operation.

The 82C37A is designed to be used with an external

address latch, such as the 82C82, to demultiplex the most

significant 8-bits of address. The 82C37A can be used with

industry standard microprocessors such as 80C286, 80286,

80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and

others. Multimode programmability allows the user to select

from three basic types of DMA services, and reconfiguration

under program control is possible even with the clock to the

controller stopped. Each channel has a full 64K address and

word count range, and may be programmed to autoinitialize

these registers following DMA termination (end of process).

FN2967

Rev 4.00

October 2, 2015

Features

• Compatible with the NMOS 8237A

• Four Independent Maskable Channels with

Autoinitialization Capability

• Cascadable to any Number of Channels

• High Speed Data Transfers:

- Up to 4MBytes/sec with 8MHz Clock

- Up to 6.25MBytes/sec with 12.5MHz Clock

• Memory-to-Memory Transfers

• Static CMOS Design Permits Low Power Operation

- ICCSB = 10A Maximum

- ICCOP = 2mA/MHz Maximum

• Fully TTL/CMOS Compatible

• Internal Registers may be Read from Software

• Pb-Free Plus Anneal Available (RoHS Compliant)

FN2967 Rev 4.00

October 2, 2015

Page 1 of 26

82C37A

Pin Description

SYMBOL

GND

CLK

NUMBER

TYPE

DESCRIPTION

: is the +5V power supply pin. A 0.1F capacitor between pins 31 and 20 is recommended for

decoupling.

Ground

CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A operations.

This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or

from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation.

CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for CPU

communications.

RESET: This is an active high input which clears the Command, Status, Request, and Temporary

registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore

requests. Following a Reset, the controller is in an idle cycle.

READY: This signal can be used to extend the memory read and write pulses from the 82C37A to

accommodate slow memories or I/O devices. READY must not make transitions during its specified set-

up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode.

HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has

relinquished control of the system busses. HLDA is a synchronous input and must not transition during

its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising edge of

CLK, during which time HLDA must not transition.

DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request inputs

used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest priority and

DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK

will acknowledge the recognition of a DREQ signal. Polarity of DREQ is programmable. RESET initializes

these lines to active high. DREQ must be maintained until the corresponding DACK goes active. DREQ

will not be recognized while the clock is stopped. Unused DREQ inputs should be pulled High or Low

(inactive) and the corresponding mask bit set.

DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus.

The outputs are enabled in the Program condition during the I/O Read to output the contents of a register

to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the CPU is

programming the 82C37A control registers. During DMA cycles, the most significant 8-bits of the address

are output onto the data bus to be strobed into an external latch by ADSTB. In memory-to-memory

operations, data from the memory enters the 82C37A on the data bus during the read-from-memory

transfer, then during the write-to-memory transfer, the data bus outputs write the data into the new

memory location.

I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input control

signal used by the CPU to read the control registers. In the Active cycle, it is an output control signal used

by the 82C37A to access data from the peripheral during a DMA Write transfer.

I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input control

signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output control

signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.

RESET

READY

HLDA

DREQ0-

DREQ3

16-19

DB0-DB7

21-23

26-30

I/O

IOR

I/O

IOW

I/O

FN2967 Rev 4.00

October 2, 2015

Page 4 of 26

82C37A

Pin Description

SYMBOL

EOP

NUMBER

(Continued)

TYPE

I/O

DESCRIPTION

END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information concerning

the completion of DMA services is available at the bidirectional EOP pin.

The 82C37A allows an external signal to terminate an active DMA service by pulling the EOP pin low. A

pulse is generated by the 82C37A when terminal count (TC) for any channel is reached, except for

channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will be output when

the TC for channel 1 occurs.

The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor to

When an EOP pulse occurs, whether internally or externally generated, the 82C37A will terminate the

service, and if autoinitialize is enabled, the base registers will be written to the current registers of that

channel. The mask bit and TC bit in the status word will be set for the currently active channel by EOP

unless the channel is programmed for autoinitialize. In that case, the mask bit remains clear.

A0-A3

32-35

I/O

ADDRESS: The four least significant address lines are bidirectional three-state signals. In the Idle cycle,

they are inputs and are used by the 82C37A to address the control register to be loaded or read. In the

Active cycle, they are outputs and provide the lower 4-bits of the output address.

ADDRESS: The four most significant address lines are three-state outputs and provide 4-bits of address.

These lines are enabled only during the DMA service.

HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus. When

a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made, the 82C37A

issues HRQ. The HLDA signal then informs the controller when access to the system busses is permitted.

For stand-alone operation where the 82C37A always controls the busses, HRQ may be tied to HLDA.

This will result in one S0 state before the transfer.

DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one has

been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them to active

low.

ADDRESS ENABLE: Address Enable enables the 8-bit latch containing the upper 8 address bits onto

the system address bus. AEN can also be used to disable other system bus drivers during DMA transfers.

AEN is active high.

ADDRESS STROBE: This is an active high signal used to control latching of the upper address byte. It

will drive directly the strobe input of external transparent octal latches, such as the 82C82. During block

operations, ADSTB will only be issued when the upper address byte must be updated, thus speeding

operation through elimination of S1 states. ADSTB timing is referenced to the falling edge of the 82C37A

clock.

MEMORY READ: The Memory Read signal is an active low three-state output used to access data from

the selected memory location during a DMA Read or a memory-to-memory transfer.

MEMORY WRITE: The Memory Write signal is an active low three-state output used to write data to the

selected memory location during a DMA Write or a memory-to-memory transfer.

NO CONNECT: Pin 5 is open and should not be tested for continuity.

A4-A7

37-40

HRQ

DACK0-

DACK3

14, 15

24, 25

AEN

ADSTB

MEMR

MEMW

FN2967 Rev 4.00

October 2, 2015

Page 5 of 26

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